Page loading . . .

  
 Category: News: Latest News: Tuesday, May 21, 2013
iC-Logic Licenses Arteris FlexNoC and C2C Interconnect IP for Automotive SOCs  
 Printer friendly
 E-Mail Item URL

May 9, 2012 -- Arteris SA today announced that iC-Logic GmbH has selected Arteris FlexNoC network-on-chip interconnect IP and C2C chip-to-chip interconnect IP for systems-on-chip (SOCs) targeting high-end automotive infotainment equipment. iC-Logic chose FlexNoC and C2C to create a flexible and high speed communication chip to respond to the increasing demand of high-speed connectivity in car infotainment systems.

"iC-Logic licensed Arteris FlexNoC and C2C because we needed fast design-cycle time and full compatibility with other SOCs. FlexNoC's ease-of-use and integrated simulation and verification features helped us to optimize our SOC integration and development time," said Martin Damrau, Managing Director at iC-Logic. "And our choice of the C2C chip-to-chip interconnect IP ensures our compatibility with application processors using C2C. Thanks to the collaboration with Arteris, iC-Logic added C2C integration expertise to our skill set enabling us to quickly design SOCs with this sophisticated interface."



Go to the Arteris SA website to find additional information.

E-mail Arteris SA for more information.

Read more about
Arteris SA
and
iC-Logic GmbH
on SOCcentral.com


Keywords: ASICs, ASIC design, IP, intellectual property, cores, on-chip interconnect, network-on-chip, NoC, Arteris, FlexNoC, iC-Logic,
601/38408 5/9/2012 599 69


Designer's Mall
0.484375



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.191  0.546875