May 14, 2012 -- Cadence Design Systems, Inc. announced today that Netronome, a developer of intelligent network flow processors (NFP), gained a significant performance advantage on its low-power SOCs by using the Cadence . In addition to increased chip performance, Netronome engineers using the latest Encounter 11.1 technology achieved a 29% reduction in power consumption, smaller design area and faster overall time-to-market compared to their former flow, for SOCs targeting the secure virtualized cloud and data center markets.

Netronome needed to optimize its high-performance 40-Gbps NFPs for low power consumption for use in its customers' switches, routers, load balancers and cyber-security platforms. Netronome engineers were tasked with improving chip power efficiencies across multi-mode, multi-corner and on-chip variation scenarios. Implementing robust clock trees that consume less dynamic switching and static leakage power without compromising on performance was difficult under such extreme requirements. Furthermore, as chip power consumption increases, it costs more to design, fabricate, operate and cool devices and systems.

"Using the complete Cadence Encounter RTL-to-GDSII flow, we were able to tape out a complex 1.4-GHz 40-core micro-engine-based Network Flow Processor on schedule, achieving a 29 percent power savings and 10 percent improvement in timing," said Jim Finnegan, Senior Vice President, Silicon Engineering at Netronome. "We were particularly impressed with the newly integrated Clock Concurrent Optimization (CCOpt) technology in the Encounter flow and its unique ability to optimize clocks and datapath simultaneously, allowing us to eliminate several manual design steps and achieve superior performance, power and area results on our design."

Traditional clock tree synthesis (CTS) tools and methodologies, which are based on minimizing skew and are isolated from logic/ physical optimization, are insufficient for advanced-node, high-performance designs due to the growing gap between pre- and post-CTS design timing. CCOpt technology bridges the gap by re-focusing CTS directly on timing, not skew minimization, and combining this timing-driven CTS with concurrent logic/ physical optimization.