June 4, 2012 -- Atrenta, Inc. today announced the availability of a Fast Lint methodology for its SpyGlass RTL analysis and optimization platform. The new capability is part of Atrenta's GuideWare reference methodology and tests on a wide range of designs have shown a 4X to 9X speed improvement while still delivering accurate, low noise results.

In addition to Fast Lint, hierarchical analysis support, which abstracts design elements that have been pre-analyzed for higher (chip-level) analysis can deliver 5X to more than an order-of-magnitude speed improvement for highly complex designs as compared to running flat (i.e., without hierarchy).

The SpyGlass linting solution analyzes a design at the register transfer level (RTL) of abstraction for coding styles and circuit constructs that can cause verification and implementation issues. Linting forms the base capability for the SpyGlass platform, which is also used widely for power optimization, clock-synchronization verification (CDC), testability, constraints management and routing-congestion analysis. Design groups use SpyGlass to verify that their designs are ready to be handed off to back-end physical implementation tools. The Fast Lint methodology allows rapid feedback during the early stages of RTL development. It is also used by revision control systems before new code check-in occurs.