June 5, 2012 -- Mentor Graphics Corp. today announced that Hitachi, Ltd. has adopted Olympus-SoC place-and-route for large scale ASIC development, and has achieved successful tape out of a 40-nm, 90-million gate design. The Olympus-SoC place-and-route platform features a patented architecture specifically created to address extremely large and complex IC designs.

"Hitachi was able to easily close timing for this large scale 90-million-gate design using the large flat-mode capacity of Olympus-SoC," said Kazuhisa Miyamoto, Senior Director, Monozukuri Innovation Group, Hitachi. "Not only did Olympus make it easier and faster to close the design, but we also got much better quality of results. Through good communication with R&D, Mentor Graphics provided us with swift support whenever we got into trouble. We believe it is truly significant for our business that we completed such a successful tape out with Olympus-SoC."

Olympus-SoC has a compact database that enables it to handle full-chip designs with hundreds of millions of gates in flat mode. This, combined with native multi-corner, multi-mode optimization, provides improved timing and signal integrity for chips with exploding gate counts and mode-corner scenarios.

The system also provides full support for multi-voltage, low-power designs including advanced algorithms for clock tree optimization and leakage reduction. The Olympus-SoC router has also been architected to handle complex design rule checking (DRC) and design-for-manufacturing (DFM) requirements for advanced process nodes, including pattern matching, and priority-based recommended rules support. The Olympus-SoC system is tightly integrated with the Calibre verification and DFM platform to address manufacturing variability with sign-off verification at the design stage.