| CEVA Leverages Synopsys Tools for Tape Out of Mixed-signal, DSP and High Speed Serial Interface Chips | | |
January 11, 2005 -- Synopsys, Inc. announced today that CEVA, Inc., a licensor of digital signal processors (DSP) cores and communications solutions, has taped out its next-generation high-speed serial interface chips and the CEVA-Teak DSP using Synopsys' Galaxy and Discovery platforms.
The CEVA design team cited Synopsys' convergent flow consisting of the following toolset as the reason for their success: Physical Compiler and Astro products for increased capacity, PrimeTime SI tool for signal integrity, Power Compiler products for power management, and VCS and NanoSim software for mixed-signal chip sign-off. The correlation of these tools was key to implementing their complex mixed-signal designs.
CEVA, a leading IP licensing company, uses the world's leading fabrication facilities to harden and prove its designs in silicon. The company chose the Synopsys Galaxy and Discovery solutions to meet the challenges it faced when designing chips for 130nm processes and below.
"We relied on Synopsys' routing and placement solutions for our 130 nanometer chips, with an eye toward future designs of 3Gbps serial interfaces that we expect to develop in a 90 nanometer process," said John Ryan, vice president of Communications and Navigation at CEVA. "Synopsys offered solutions that were both technically advanced and cost efficient for our future low-power and mixed-signal designs. We look forward to continued success using Synopsys platforms to produce our advanced mixed-signal and communications devices."
Go to the Synopsys, Inc. website to find additional information.
| E-mail Synopsys, Inc. for more information.
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| Keywords: Synopsys, CEVA, intellectual property, IP, DSP, Physical Compiler, Astro, PrimeTime, VCS, NanoSim, Galaxy, Discovery,
| | 199/10979 1/11/2005 1514 254 | |
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