Page loading . . .

  
 Category: News: News Archive 2005: Thursday, May 23, 2013
Spartan-3 and Virtex-II Pro FPGAs Win Multiple Designs in Mangrove MPLS Platforms  
 Printer friendly
 E-Mail Item URL

February 22, 2005 -- Xilinx, Inc. announced today that Mangrove Systems, a provider of metro and access network infrastructure, has selected Xilinx 90nm Spartan-3 and Virtex-II Pro FPGA devices for use in its latest Piranha and Barracuda MetroMPLS (Multiprotocol Label Switching) Platforms. Combining Metro Ethernet Forum services, MPLS pseudowires, multi-service support and new efficient data-over-transport standards, the Mangrove product family enable carriers to transform existing SONET and SDH infrastructure into efficient, packet-aware metro and access networks.

Mangrove selected Spartan-3 FPGAs based on an exhaustive evaluation that covered price, performance, packaging that included high I/O count and density along with vendor commitment. Mangrove also chose Xilinx Virtex-II Pro FPGAs with embedded PowerPC processor and Multi Gigabit Transceivers (MGTs) for control plane functions and backplane interconnect.

Mangrove engineers optimized the use of a single design platform, Xilinx ISE (Integrated Software Environment) 6.3i, allowing easy portability of projects between their various design teams. Xilinx ISE design tools are optimized to make very efficient use of internal device features, significantly reducing overall development costs and time-to-market.

"The incorporation of Xilinx technology into our MetroMPLS platforms has enabled Mangrove to raise the bar on performance and define a new level of integration for the Metro and Access infrastructure," said Jonathan Reeves, Mangrove president and CEO. "The deployment of Fiber to the Home and migration to 3G wireless infrastructures requires higher bandwidth solutions at lower price points both of which the Xilinx technology helps us to achieve."

Go to the Xilinx, Inc. website to find additional information.

Read more about
Xilinx, Inc.
on SOCcentral.com


Keywords: Xilinx, Mangrove Systems, Spartan-3, Virtex-II, FPGAs, PowerPC, platform FPGAs,
199/11790 2/22/2005 1431 222


Designer's Mall
0.375



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.199  0.453125