April 20, 2005 -- Atmel Corp. has announced today the availability of the ATU18, a complete set of 0.18 micron structured array matrices to convert most FPGA/CPLDs with Atmel's Ultimate Logic Conversion (ULC), enabling significant cost savings for system makers.

With the ATU18 matrices, Atmel can handle up to 1,200 K-bits Dual Port RAM, 1,600K gates, PLLs, and Multipliers in a single chip. These memory blocks are compatible with embedded memory blocks from FPGA/CPLD makers Xilinx and Altera. The 51micron pad pitch allows significant reduction of die size even for high pin count conversions that are often pad limited. The Atmel ULC design flow has been improved to handle the latest FPGA architectures, resulting in a shorter conversion lead-time.

Atmel's ATU18 solution uses only wafer metal layers to configure the ULC, offering very low non-recurring engineering (NRE) charges compared to solutions that require a full mask set. By removing the silicon area needed for programmability and implementing the memory in ULC memory blocks, Atmel can significantly reduce the size of the die and can bring up to 80 percent cost savings for the latest FPGAs with a pin-to-pin compatible offer.

With its 0.18 micron process, Atmel ULC's can support complexities equivalent to 8,000K FPGA gates. The ULC's internal frequency can be run at a much faster speed than that with conventional FPGAs, with at least 200 MHz. Power consumption can typically be 70 percent lower than its FPGA counterpart.

Pricing and Availability