April 20, 2005 -- Synopsys, Inc. has announced that Top Layer Networks, a provider of high-performance intrusion-prevention solutions, used Synopsys' Vera testbench automation tool to verify the chip at the heart of the Attack Mitigator IPS 5500 family of intrusion prevention solutions (IPS). The advanced features of the Vera tool and Synopsys' Reference Verification Methodology (RVM) enabled the Top Layer team to improve its process for detecting and fixing design bugs before tapeout to ensure the integrity of the final product.

"There was no doubt that Synopsys' Vera testbench automation solution was the right choice for our verification environment," said Jay Brown, verification manager at Top Layer. "Our customers rely on our products to safeguard their networks from zero-day exploits, denial-of-service (DoS) attacks, worms, spyware, email viruses and other threats. The thorough verification provided by the Vera tool and the RVM allowed us to design an industry-leading product that helps prevent malicious content from slipping through the cracks."

In order to improve its traditional VHDL-based approach, Top Layer evaluated competing testbench automation solutions in the market. The company selected the Vera tool for several key reasons, including its support for constrained-random stimulus generation, functional coverage and other advanced verification methods. They also chose the Vera tool for its extensive RVM guidelines and documentation, which allow faster setup of the verification environment. Synopsys' support for SystemVerilog, including assertions, coverage and testbench capabilities, was also a key factor in the decision since this standard will be important for future Top Layer projects.