August 23, 2005 -- Analog Devices, Inc. (ADI) has announced the availability of its new ADIsimCLK clock IC design and simulation tool, along with the addition of three new clock ICs to its portfolio of clock products. ADIsimCLK offers clock and timing engineers an easy-to-use simulation tool for designing and analyzing clock circuits used in a broad range of applications, such as wireless transceivers, broadband infrastructure, medical imaging, general instrumentation, and automated test equipment. By using the tool's tutorials, design wizards, and user-friendly data entry screens, engineers can quickly create complete, robust timing solutions. And because ADIsimCLK models the phase noise and jitter of the components used, final system performance can be predicted with great accuracy, allowing designers to move from simulations to final board layouts faster, removing iterations from the design process and speeding time to market.

The availability of ADIsimCLK coincides with the introduction of Analog Devices' newest clock IC family members - the AD9513, AD9514 and AD9515 - that extend output clock rates to 1.6GHz. The new pin-programmable ICs feature high integration in small packages to eliminate the need for multiple discrete components, save on board space, and ultimately reduce BOM (bill of materials) costs. Like preceding members of Analog Devices' AD95xx clock family, the new clock ICs feature ultra-low jitter performance which can improve SNR (signal-to-noise ratio) by 6 to 12dB in wireless infrastructure, instrumentation, and broadband networking systems.

"Use of low-phase-noise, low-jitter clock ICs reduces overall noise in a signal path," said Kevin Kattmann, product line director, High Speed Converters, Analog Devices. "However, optimizing clock solutions can be painstaking and time consuming. The ADIsimCLK tool was created to simplify the clock distribution design process by allowing customers to analyze and test critical timing circuits before committing to hardware, reducing risk and shortening development time. The ICs introduced today help designers who need a better way to distribute low jitter clocks across a crowded PCB to multiple sub-circuits. Designers can now route common clock frequencies up to 1.6GHz to the AD9513/14/15, which perform divides, phase offsets, and delays in close proximity to the circuits needing clocks. The small packages allow customers to save on board space and cost, while improving their overall system performance."

Based on ADI's ADIsimPLL tool for low-phase-noise PLL synthesizer design, ADIsimCLK can simulate jitter of less than 1 picosecond rms and phase noise less than -150dBc/Hz. ADIsimCLK simplifies loop filter design and optimization and lets designers test the functionality and performance of Analog Devices' family of low jitter clock ICs without touching any hardware.

The tool features a data panel that allows designers to alter loop bandwidths, change charge pump currents, set divide ratios, adjust delays, and choose output drivers. The tool's result panel displays overall frequency response, timing diagrams, schematics, and provides detailed performance data on each individual clock output. Equipped with a library of references, VCOs and VCXOs, ADIsimCLK lets the designer observe exactly how each component affects the clock distribution design at the touch of a button.

Packaged in a small 32-lead LFCSP (lead frame chip scale package), the AD9513, AD9514 and AD9515 can be placed close to devices requiring clocks. All three products feature 4-level logic pins that are used to program divide ratios, phase offsets, delays and output logic levels. This pin programmability means that no serial port is required for device setup, making it easy for designers to drop the new ICs into existing circuits. All that is required for operation is a single +3.3V supply.

Like other members of the AD95xx family, the AD9513, AD9514 and AD9515 improve a system's overall noise performance by maintaining additive jitter levels of less than 300fs (femtoseconds) rms. Superior clock output isolation greatly reduces susceptibility to noise.

ADI's distribution ICs feature LVPECL outputs, as well as user-selectable LVDS (low-voltage differential signaling) and CMOS options. All three products feature divide ratios in the range of 1 to 32, and user-selectable phase offsets. LVPECL outputs operate up to 1.6GHz with additive jitter of just 225fs rms.

Pricing and Availability