November 28, 2005 –- Infineon Technologies AG has announced availability of an advanced hard disk drive read channel core, the first integrated circuit implemented in the company’s 90-nm process technology. Developed in cooperation with Hitachi Global Storage Technologies (Hitachi GST), the read channel core is a milestone on the path to developing high-integration controller chips for next generation hard disk drives.

"With its first 90-nm read channel product Infineon is well on track to deliver the next generation of ICs for the growing HDD market," stated Peter Bauer, member of the management board and head of Infineon’s Automotive, Industrial and Multimarket business group.

"Migration to 90nm of the Infineon read channel core enables the HDD industry to meet next generation product requirements, including higher data rates, reduced power consumption and smaller die-size leading to advanced SOC solutions at competitive cost. The first tested read channel core silicon has demonstrated that the PLL is able to reach up to 3.6-GHz speed and that the analog front-end signal path allows for datarates up to 2.7Gb/s. This is an increase of approx. 50% compared to advanced Read Channels in 130-nm technologies,” said Sandro Cerato, General Manager and Vice President at Infineon ADS - ASIC and Design Solutions.

The new read channel technology generation supports advanced features such as perpendicular recording and leverages on 2nd generation reverse concatenation coding to deliver state-of-the-art signal-to-noise-ratio (SNR) performance for significantly improved storage densities.

Infineon’s 90nm read channel technology leverages on a common architecture and is applicable to all HDD segments (Enterprise, Desktop, Mobile and Ultra-Low-Power). The requirements of the different HDD platforms are achieved by customizing the designs to the specific target parameters of each market segment.

A second implementation, currently in development for battery operated applications, targets an exceptionally low power dissipation. It will also provide superior stand-by power and leakage current performance thanks to Infineon’s 90nm process technology that is designed to support handheld applications such as cellular phones.

The new read-write channel has been implemented in Infineon's 90-nm CMOS technology which provides the capabilities of combining high performance, low power and analog devices in the same silicon for various applications. Infineon's technology and design system allows for product specific and cost effective optimizations for mixed signal and advanced digital signal processing in a single chip ranging from performance intensive enterprise-class server applications to power sensitive mobile consumer electronic applications. Key features of the technology are the ability to integrate multiple threshold voltages and multiple gate oxide devices with minimum physical gate dimensions down to 70nm using advanced power saving concepts like active wells, clock-gating and micro-switches with 6 to 9 layers of copper metallization in a single chip.