| Toshiba Adopts Synopsys IC Compiler for Use in Its SoC Research and Development Center |
June 7, 2005 -- Synopsys, Inc. today announced that Toshiba Corp. is adopting Synopsys IC Compiler for use in its System-on-chip Research and Development Center. A centerpiece of Synopsys Galaxy Design Platform, the IC Compiler physical impleme ... read more |
| Denali Software, GDA Technologies Team to Deliver Comprehensive IP Solutions for Advanced Switching Interconnect Systems |
June 7, 2005 -- Denali Software, Inc. and GDA Technologies have announced a cooperative effort to deliver a comprehensive intellectual property (IP) platform for chip developers implementing the Advanced Switching Interconnect (ASI) standard. Le ... read more |
| Accelerated Technology Upgrades Eclipse-Based Nucleus EDGE Environment for Embedded Developers |
June 7, 2005 -- Accelerated Technology, a division of Mentor Graphics Corp. has added new features and capabilities to its Eclipse-powered Nucleus EDGE software development environment. Features such as extended kernel awareness, a new debug cha ... read more |
| Agilent Technologies Announces 64-Bit 3D-Planar Electromagnetic Modeling Software |
June 7, 2005 -- Agilent Technologies, Inc. has introduced a 64-bit version of Momentum, its 3D-planar electromagnetic software. The release offers significantly improved accuracy, capacity and speed for design and verification of passive compone ... read more |
| Synopsys DFM Environment Selected by TI for Design and Process Development for the 65-nm Node and Beyond |
June 7, 2005 -- Synopsys, Inc. today announced that Texas Instruments (TI) has adopted the Synopsys design-for-manufacturing (DFM) environment for its 65nm and beyond designs. TI extended its use of Synopsys' Alternating Aperture Phase Shift Mas ... read more |
| Altera Announces DSP Development Kit Based on Stratix II |
June 7, 2005 -- Altera Corp. has announced the availability of a new digital signal processing (DSP) development kit that includes a development board based on the Stratix II EP2S180 device. The Altera development kit includes Quartus II softwar ... read more |
| Accelerated Technology Upgrades Eclipse-based Nucleus EDGE Environment for Embedded Developers |
June 7, 2005 -- Accelerated Technology, a Mentor Graphics division, has added new features and capabilities to its Eclipse-powered Nucleus EDGE software development environment. Features such as extended kernel awareness, a new debug channel and ... read more |
| Xilinx Announces Shipments of Virtex-4 FX60 FPGAs with 622Mbps - 10.3125Gbps Serial Transceivers |
June 6, 2005 -- Xilinx, Inc. has announced initial customer shipments of its Virtex-4 FX60 90nm FPGAs with integrated 622Mbps - 10.3125Gbps serial transceivers. Among the first customers to receive initial Virtex-4 FX60 devices is Spirent Commun ... read more |
| Synopsys Enables Rapid Adoption of SATA Interface with DesignWare Verification IP |
June 6, 2005 -- Synopsys, Inc. has announced the addition of Serial ATA (SATA) verification intellectual property (VIP) to its DesignWare Library. System-on-chip (SoC) designers now have access to high-quality, high-performance SATA VIP to verif ... read more |
| Bellum Software Offers Architecture Workbench for System Engineers |
June 6, 2005 -- Bellum Software has announced the availability of its first product - Protocollum - a visual tool for high-end design and protocol mapping for electronic system designs, such as large ASICs and full custom chips. The new tool, Pr ... read more |
| Magma Introduces Quartz DRC |
June 6, 2005 -- Magma Design Automation, Inc. has announced the availability of Quartz DRC, a key component of Magma's recently announced Cobra 2005.03 release and a result of Magma's acquisition of Mojave Design. Quartz DRC is architected to pr ... read more |
| Magma Developing 65-nm Quartz DRC Runset for IBM Processes |
June 6, 2005 -- Magma Design Automation, Inc. today announced that IBM has been evaluating Quartz DRC Design Rule Files for its 90nm and 65nm foundry processes. Quartz DRC is a key component of Magma's recently announced Cobra 2005.03 release an ... read more |
| Apache Introduces PsiWinder, a Combined Power and Signal Integrity Timing Sign-off Tool |
June 6, 2005 -- Apache Design Solutions, Inc. has unveiled PsiWinder, a critical path and clock tree analysis tool that considers crosstalk and dynamic power integrity effects on a chips' timing. For designs at 90nm and 65nm processes, the quali ... read more |
| Sagantec Releases Tool Set Supporting 65nm and 45nm Process Design Rules |
June 6, 2005 -- Sagantec, Inc. has released Sagantec Tool Set version 8 (STS8) which is capable of supporting 65nm and 45nm technology design rules, has been used to deliver 65nm silicon, and is being used in an early 45nm engagement. Large data ... read more |
| Giga Scale IC Introduces IC Economic Analysis Engine |
June 6, 2005 -- Giga Scale IC, Inc. has introduced the industry's first comprehensive IC economic analysis engine. The feature is now available as an upgrade to the company's InCyte chip estimation tool, which can be downloaded in a free, time-u ... read more |
| STMicroelectronics Adds DSP to Reconfigurable-Processor SoC for Wireless Infrastructure Applications |
June 6, 2005 -- STMicroelectronics has disclosed details of an enhanced version of its recently announced STW21000, a multi-purpose microcontroller that targets applications in wireless infrastructure equipment. Fabricated using ST’s 130nm CMOS ... read more |
| Xilinx Announces Immediate Availability of 4 Gbps Programmable Fibre Channel Core |
June 6, 2005 -- Xilinx, Inc. today announced the immediate availability of a 4 Gbps programmable Fibre Channel solution. Designed specifically for the Virtex-4 FPGA family, the new 4G Fibre Channel core provides system architects with the abilit ... read more |
| Synopsys Announces DesignWare IP Support for PCI Express 1.1 Specification |
June 6, 2005 -- Synopsys, Inc. has announced that its DesignWare IP for PCI Express supports the recently released PCI Express 1.1 specification, which includes several errata updates and improvements to increase the robustness of power manageme ... read more |
| VSI Alliance Releases New Version of Quality IP Metric Featured |
June 6, 2005 -- The VSI Alliance (VSIA) has just released the VSIA QIP Metric 2.0, developed by VSIA and FSA member companies. These semiconductor, EDA and semiconductor Intellectual Property (SIP) providers developed the metric to address the n ... read more |
| The Open SystemC Initiative Announces Availability of the SystemC Transaction-level Modeling Standard Featured |
June 6, 2005 --The Open SystemC Initiative (OSCI) today announced the delivery of the SystemC Transaction-Level Modeling (TLM) Standard 1.0. The new TLM standard defines application programming interfaces (APIs) and provides a library that imple ... read more |
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