Page loading . . .

  
 Category: News: News Archive 2005: Wednesday, June 19, 2013
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 (1910 Entries)
OEA International Enhancements Its Spiral Inductor Design and Synthesis Tool 

June 1, 2005 -- OEA International, Inc. has announced a new update to Spiral, a 3D inductor design toolset for designing and synthesizing on-chip inductors in analog and RF chips. By providing a simple set of performance and physical specificat ... read more

Actel Broadens PCI Product Family with CorePCIF 

June 1, 2005 -- Actel Corp. has introduced CorePCIF, the newest member of the company's PCI product family that also includes CorePCI and CorePCIX. CorePCIF incorporates netlist and register transfer level (RTL) versions with 33 and 66MHz speed ... read more

Zuken 3D Routing Checker Cuts Design Time for Higher Voltage Printed Circuit Boards 

May 31, 2005 -- Zuken, Ltd. has introduced Spacing Synthesizer, a 2D and 3D routing checker for high voltage printed circuit boards (PCBs), such as those carrying power supply circuits or boards designed for intrinsically safe applications, that ... read more

Sigrity Tools Optimize IR Drop Analysis for Packages and Boards 

May 31, 2005 -- Sigrity, Inc. today announced PowerDC PKG and PowerDC PCB - software customized for system-level IR drop analysis. As a standalone tool optimized for IR drop analysis for packages and boards, it helps designers budget end-to-end ... read more

Accellera Approves New Version of Co-Emulation Modeling Interface Standard 

May 31, 2005 -- Accellera's board of directors, representing systems, semiconductor and design tool member companies, has approved Accellera's Standard Co-Emulation Modeling Interface (SCE-MI) 1.1 as an Accellera verification standard. The SCE-M ... read more

OCP-IP Signs Five New Members 

May 31, 2005 -- Open Core Protocol International Partnership (OCP-IP) announced today that five new members are joining the organization: ASICS World Services, Atrenta, Celoxica, First Silicon Solutions (FS2) and Jeda Technologies. The new membe ... read more

Huawei Adopts Synopsys VCS Native Testbench to Accelerate Verification of Networking and Communications ASICs 

May 31, 2005 -- Synopsys, Inc. today announced that Huawei Technologies, a global networking and communications equipment company, has adopted Synopsys' VCS comprehensive RTL verification solution with Native Testbench (NTB) technology and comp ... read more

Synopsys Adds Assertion IP Library and Native Testbench Support for SystemVerilog to VCS 

May 31, 2005 -- Synopsys, Inc. is incorporating a number of new capabilities into its VCS comprehensive RTL verification solution that let engineers find more design bugs faster and achieve up to five times faster verification performance. The V ... read more

Virage Logic Joins with TSMC to Lead 65nm Ramp 

May 31, 2005 -- TSMC has tapped Virage Logic Corp. to develop libraries in support of early users of TSMC's 65nm Nexsys process technology. The agreement provides IC designers with much-needed memory compilers for leading-edge system-on-chip (So ... read more

TransEDA Unveils Assertain Verification Closure Management Tool 

May 30, 2005 -- TransEDA, has announced the launch of Assertain, a Verification Closure Management (VCM) tool that the company ways delivers, in a single environment, total measurement and control of the digital design verification process. Inde ... read more

Averant Announces Release of Solidify, Version 3.1 

May 27, 2005 -- Averant, Inc. has released Solidify 3.1, providing extensive enhancements to performance and usability. The Solidify property verification tool includes fast and comprehensive engines, patented coverage technology, patent-pending ... read more

Mentor Graphics Strengthens Its Automotive Solutions Portfolio with Acquisition of Volcano Communications Technologies 

May 26, 2005 -- Mentor Graphics Corp. has acquired Volcano Communications Technologies AB (VCT), including the complete product line of Volcano's automotive networking series. The series includes network design tools, embedded software and test ... read more

Poseidon Joins LSI Logic RapidChip Platform ASIC Partner Program 

May 26, 2005 -- Poseidon Design Systems, Inc. has joined the LSI Logic RapidChip Platform ASIC Partner Program, which offers designers the methodology, IP and technology to develop advanced, next generation solutions. Poseidon's Triton tool sui ... read more

Aprio's New Design-Side Technology Aims to Unifying Semiconductor Design and Manufacturing 

May 26, 2005 -- With the Halo suite of design-for-manufacturing (DFM) tools already receiving a warm reception from manufacturing-side users, Aprio Technologies, Inc. announced that it will give Design Automation Conference (DAC) attendees an ad ... read more

Mentor Graphics Achieves PCI Express Intellectual Property Compliance on NitAl Platform 

May 26, 2005 -- Mentor Graphics Corp. today announced it is the first third-party intellectual property (IP) vendor to achieve PCI Express specification compliance on the NitAl PExBuilder-X254 Platform. Compliance, which includes vigorous intero ... read more

Denali Announces Dataplex IP Product for DDR, Flash, and SATA Subsystems  

May 25, 2005 -- Denali Software, Inc. has announced Dataplex, a new data-subsystem IP product for DRAM, Flash and hard disk drive interfaces. With this announcement, Denali gives chip designers access to a single IP solution that controls off-ch ... read more

French Startup EdXact to Introduce Jivaro Twins 

May 25, 2005 -- EdXact will introduce two versions of its standalone netlist reduction tool, Jivaro, at the Design Automation Conference (DAC) in Anaheim. Jivaro-A for analog and RF circuits, and Jivaro-D for digital and mixed-signal circuits, a ... read more

Altera Joins WiMAX Forum 

May 25, 2005 -- Altera Corp. has joined the WiMAX Forum, an industry-led, non-profit organization formed to promote and certify compatibility and interoperability of broadband wireless products based on the IEEE 802.16 standard.

Ron Resnic ... read more

Initial IP Support for New LatticeXP FPGA Family Now Available 

May 25, 2005 -- Lattice Semiconductor Corp.has announced the immediate availability of several key ispLeverCORE intellectual property (IP) modules for its recently announced LatticeXP FPGAs. Optimized to take full advantage of the LatticeXP arc ... read more

Electronics Workbench Launches Ultiboard 8 And Ultiroute 8 for PCB Layout and Autorouting 

May 25, 2005 -- Electronics Workbench Corporation, a National Instruments company, has launched Ultiboard 8 and Ultiroute 8. These major releases complete the Electronics Workbench Series 8 Design Suite, allowing users to efficiently and seamles ... read more




 Search for:
            Site       Current Category  
   Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.199  3.328125