| Marvell Implements High-Speed, High-Volume Communications Designs with Magma's Blast Create and Blast Fusion |
January 24, 2005 -- Magma Design Automation, Inc. today announced that Marvell Technology Group, Ltd. has achieved silicon success on several designs using Magma's Blast Create and Blast Fusion software. Marvell selected Magma's software as an ... read more |
| Averant Announces SolidTC Timing Constraints Verifier |
January 24, 2005 -- Averant, Inc. has announced the availability of SolidTC, a fully automatic verifier for timing exceptions, based on Averant's formal verification tool Solidify and augmented with new algorithms designed for this task.
read more |
| MoSys Signs Sales Representative Agreement with China's Crescendo Technologies |
January 24, 2005 -- Monolithic System Technology, Inc. has signed Crescendo Technologies, Ltd. of Shanghai, PRC, as an authorized sales representative for MoSys in China.
Crescendo Technologies is an electronics design solutions compan ... read more |
| Magma Announces PALACE Support for Actel's Flash-Based ProASIC3 and ProASIC3E FPGAs |
January 24, 2005 -- Magma Design Automation, Inc. has announced that Magma's PALACE software design tool for programmable logic supports Actel's new high-speed, low-cost, third-generation flash-based ProASIC3 and ProASIC3/E FPGA families. Fully ... read more |
| IBM and Chartered Extend Technology Development Agreement to 45 Nanometer |
January 24, 2005 -- IBM and Chartered Semiconductor Manufacturing,Ltd. have signed an extension to their existing technology agreement, formally expanding their joint development efforts to 45nm bulk CMOS process technology. Upon the completio ... read more |
| MoSys Strengthens Presence in Taiwan |
January 24, 2005 -- To respond to increasing demand for its products in Taiwan, MoSys, Inc. has signed a sales representative agreement with Terasic Technologies, Inc.
Terasic Technologies focuses on providing ASIC verification platforms ... read more |
| Toshiba Achieves 40% Power Reduction in Latest Media Embedded Processor Using Synopsys Galaxy Design Platform |
January 24, 205 -- Synopsys, Inc. announced that Toshiba Corp. has achieved a 40 percent power reduction on its latest 90nm Media embedded Processor (MeP) system-on-chip (SoC) design using the Synopsys Galaxy Design Platform. The Galaxy platform ... read more |
| SilTerra to Provide Virage Logic's IPrima Foundation Platform to Its 130nm Process Customers |
January 24, 2005 -- SilTerra has licensed the IPrima Foundation IP platform from Virage Logic Corp. for its customers. Virage Logic's IPrima Foundation contains memory, logic and I/Os that are optimized to SilTerra's 130nm process to attain sup ... read more |
| Virage Logic Expands Distribution Model |
January 24, 2005 -- In response to emerging foundries' desire to increase their market share at 130nm, Virage Logic Corp. has expanded its distribution model with a "Foundry Pays" model that enables emerging foundries to license Virage Logic's ... read more |
| Virage Logic Launches 'Silicon Aware IP' to Maximize Yield, Time-to-Volume at 130nm and Below |
January 24, 2005 -- Virage Logic Corp. today announced its Silicon Aware IP initiative. Silicon Aware IP is Physical IP, such as memories, logic and I/Os, designed with embedded Infrastructure IP for test, diagnostics, repair, and yield enhancem ... read more |
| Tensilica’s Xtensa LX Processor Wins Microprocessor Report Analysts’ Choice Award |
January 24, 2005 –- Tensilica, Inc. today announced that its Xtensa LX processor has won the 2004 Microprocessor Report (MPR) Analysts’ Choice Award for Best Intellectual-Property (IP) Core. MPR selected the Xtensa LX core for its performance ... read more |
| Tensilica V6 Automation Tools Speed SOC Design |
January 24, 2005 – Tensilica, Inc. has announced its V6 suite of automation tools, which significantly speed the design of major blocks in system-on-chip (SOC) design, making it easier and faster to design SOCs with configurable processors than ... read more |
| CoWare Integrates SPW into Cadence System-to-IC Flow |
January 24, 2005 -- CoWare, Inc. has announced the integration of its SPW digital signal processing application design tool with new Cadence capabilities for RF designers built upon its Virtuoso custom design platform. The tight technology inte ... read more |
| Cadence Introduces New Mixed-Signal and RF Capabilities to Address Wireless Design Challenges |
January 24, 2005 -- Cadence Design Systems, Inc. has announced new capabilities that enable wireless chip designers and manufacturers to have better insight into the mixed-signal and radio frequency (RF) challenges that significantly impact wir ... read more |
| Altera Unveils HardCopy II Structured ASIC Solution Featured |
January 24, 2005 -- Altera Corp. today announced the HardCopy II family, its next-generation structured ASIC solution. HardCopy II devices are a compelling structured ASIC solution, featuring a unique FPGA front-end design methodology and costs ... read more |
| Altera Low-Cost Cyclone II FPGAs Begin Shipping Early |
January 21, 2005 -- Altera Corp. has announced that the first member of the new Cyclone II family, the EP2C35, is shipping ahead of schedule. With up to 68K logic elements (LEs) at a cost of $0.66 cents per thousand, Altera claims that the Cyclo ... read more |
| Ansoft Enhances Maxwell SV |
January 20, 2005 -- Ansoft Corp. has released an enhanced version of Maxwell SV, adding to its existing line of SV (student version) software. Maxwell SV is a free, downloadable, subset of Maxwell 2D, Ansoft's commercial electromagnetic-field s ... read more |
| Lattice ispLEVER-Starter Design Tools Now Support Selected LatticeEC FPGA Devices |
January 20, 2005 -- Lattice Semiconductor Corp. has announced the immediate availability of Version 4.2 of its web-downloadable ispLEVER-Starter programmable logic design tool suite. The ispLEVER-Starter tools are a complete programmable logic ... read more |
| Celoxica Joins Synopsys in-Sync Program for Verification and Implementation |
January 20, 2005 -- Celoxica, Inc. today announced design flow development through the Synopsys in-Sync program. This development formalizes the interoperability between Celoxica's Agility Compiler and DK Design Suite with the Design Compiler s ... read more |
| eASIC’s Structured ASIC Selected as DesignVision Award Finalist |
January 20, 2005 – eASIC Corp.'s Structured eASIC product was selected as a DesignVision Award finalist by The International Engineering Consortium (IEC). The Structured eASIC was selected for the category of "Structured/Platform ASIC, FPGA, ... read more |
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