Virtex FPGAs provide dedicated on-chip blocks of 4096-bit dual-port synchronous RAM (block SelectRAM memory). The block SelectRAM feature is ideal for use in FIFO applications. This application note describes how to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a FIFO for data-width conversion with different width read and write data ports. Introduction This application note is an enhancement to XAPP131 (170MHz Synchronous and Asynchronous FIFOs using the Virtex block SelectRAM memory). In general, only the changes from XAPP131 will be covered. The reader is strongly encouraged to read XAPP131 before proceeding. Four different data-width conversion FIFOs are described in this document. The first has a common clock with a 255 x 16 write port and a 1020 x 4 read port. The second has a common clock, a 1020 x 4 write port, and a 255 x 16 read port. The last two are similar FIFOs with independent read and write clocks. The signal names appearing in parentheses reference the names in the Verilog code.

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