| Combining Impulse C with uClinux for MicroBlaze-based FPGAs |
| Source: Impulse Accelerated Technologies, Inc. |
Using a small-footprint, open-source operating system such as uClinux can dramatically increase the power and flexibility of FPGA embedded processors. An operating system on an embedded “soft” processor can provide access to standard hardware devices p ... read more |
| Common Switch Interface CSIX-L1 Reference Design |
| Source: Xilinx, Inc. |
This application note describes a Virtex-II device implementation of a CSIX-L1 common switch interface between a network processor's traffic manager and the switching fabric for ATM, IP MPLS, Ethernet and similar data communications applications. This ... read more |
| Considerations and Options in Using Flip Chip Packages |
| Source: Amkor Technology, Inc. |
Flip chip interconnect is beginning to appear in a variety
of package formats. Early discussions of flip chip in
package (FCIP) often revolved around a simple package
concept, generally patterned after classic C4 ceramic
packaging, with the primary ... read more |
| Data-Width Conversion FIFOs Using Block SelectRAM Memory |
| Source: Xilinx, Inc. |
Virtex FPGAs provide dedicated on-chip blocks of 4096-bit dual-port synchronous RAM (block SelectRAM memory). The block SelectRAM feature is ideal for use in FIFO applications. This application note describes how to create a common-clock (synchronous) ... read more |
| Data-Width Conversion FIFOs Using the Virtex-II Block RAM Memory |
| Source: Xilinx, Inc. |
Virtex-II FPGAs provide dedicated on-chip blocks of 18 Kb dual-port synchronous RAM (block RAM). The block RAM feature is ideal for use in FIFO applications. This application note describes how to create a common-clock (synchronous) version and an inde ... read more |
| Design Tips for Arithmetic Functions |
| Source: Xilinx, Inc. |
This application note and reference design provides design advice for implementing arithmetic logic functions in two High-Level Design Languages (HDLs), VHDL and Verilog. This application note discusses design considerations for HDL coding of simple ar ... read more |
| Designing Convolutional Interleavers with Virtex Devices |
| Source: Xilinx, Inc. |
The convolutional interleaver technique is used in telecommunication applications such as SDH and PDH radio systems, GSM and UMTS mobile communication systems, and point-to-multipoint radio systems to protect transmission channels from noise. On the tr ... read more |
| Designing Flexible Fast CAMs with Virtex Family FPGAs |
| Source: Xilinx, Inc. |
Content Addressable Memories (CAM) allow a fast search for specific data in a memory. Each application has different CAM requirements. A CAM design implemented in Virtex Family slices offers a flexible approach to CAM depth and width based upon LUTs co ... read more |
| Designing State Machines for FPGAs |
| Source: Actel Corp. |
The traditional methodology for designing state machines has been to draw a state diagram, map the states into the minimum number of register bits, and determine the next state function for each register bit. The minimum number of
register bits needed ... read more |
| DesignWare SATA AHCI Host Controller: Understanding Multi-Port Configuration and Performance |
| Source: Synopsys, Inc. |
This application note describes how to configure and connect the DesignWare® SATA AHCI IP core to the Synopsys PHY in a multi-port AHB-based configuration, and provides an analysis of the expected throughput on each port based on assumed system paramet ... read more |
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