| Virtex-II Pro 3.3V PCI Reference Design |
| Source: Xilinx, Inc. |
This application note describes the Virtex-II Pro 3.3V PCI solution.
... read more |
| Virtex-II Pro RAID-5 Parity and Data Regeneration Controller |
| Source: Xilinx, Inc. |
A Redundant Array of Independent Disks (RAID) array is a disk array where part of the physical storage capacity is used to store redundant information about user data stored on the remainder of the storage capacity. The redundant information enables re ... read more |
| Virtex-II SelectLink Communications Channel |
| Source: Xilinx, Inc. |
The Virtex-II SelectLink communications channel utilizes special features of the Virtex-II series of FPGAs, including Digital Clock Managers (DCMs), block SelectRAM+ memory, and the SelectI/O interface, to create a system to move large amounts of data ... read more |
| Virtex-II SiberBridge |
| Source: Xilinx, Inc. |
Designed to be implemented in a Virtex-II FPGA,the Virtex-II SiberBridge is a register transfer logic (RTL) design example demonstrating a reference interface between a 32-bit host(typically a network processor) and the SiberCAM device, or a cascade of ... read more |
| Virtex-II SiberBridge |
| Source: Xilinx, Inc. |
Designed to be implemented in a Virtex-II FPGA,the Virtex-II SiberBridge is a register transfer logic (RTL) design example demonstrating a reference interface between a 32-bit host(typically a network processor) and the SiberCAM device, or a cascade of ... read more |
| Wireless Transceiver |
| Source: Xilinx, Inc. |
This application note focuses on the design of a wireless transceiver which consists of two modules; receive and transmit. One CoolRunner demo board comprises the receive portion while the second demo board comprises the transmit portion. The wireless ... read more |
| Word Alignment and SONET/ SDH Deframing |
| Source: Xilinx, Inc. |
This application note describes the logic to perform basic word alignment and deframing specifically for SONET/SDH systems, where data is being processed at 16-bits or 64-bits per clock cycle.
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