In the context of digital ICs, the phrase design for manufacture (DFM) refers to a variety of techniques used during the process of creating the design so as to facilitate its being manufactured. Meanwhile, the term "yield" refers to the number of die that work as a percentage of the total number of die on the silicon wafer; hence, the phrase design for yield (DFY) refers to any techniques used to improve the yield of a particular device. In reality, these concepts and techniques are so intertwined that it is becoming common to consider them as being a single DFM/DFY entity.

There have been some efforts with regard to DFM/DFY random (statistical) yield; to date, however, almost all of the focus on systematic yield issues has been in the area known as front end-of-line (FEOL). (The concepts of random and systematic yield are introduced later in this paper.) FEOL encompasses the diffusion, poly, and contact layers forming the transistors; that is, everything below metal layer 1. At the 90 nanometer node, however, the routing in the metal layers is becoming a significant systematic yield issue which no one has addressed thus far. As we move to the 65 nanometer node and below, routing will become a major yield limiter for designs.