SOCcentral: Interoperable IP Delivery (Aldec, Inc. 34165)

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Saturday, May 25, 2013

Interoperable IP Delivery

Company: Aldec, Inc.

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This paper describes the theoretical background, current status and future challenges facing interoperable cryptosystem for safe delivery of Intellectual Property (IP) to be used in VHDL and SystemVerilog design and verification. The system must be reliable, and interoperable, i.e., enable safe use of IP source in a variety of tools. IEEE P1735 Working Group currently develops proposed standard describing such a cryptosystem.

Access the entire document on the Aldec, Inc. website.

E-mail Aldec, Inc. for more information.

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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification, IP, intellectual property, cores, VHDL, SystemVerilog, Aldec,

205/34165 6/24/2011 1720 118

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