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 Category: Tutorials, White Papers, App Notes, etc.: White Papers: Monday, May 20, 2013
Variation Analysis and Design for Custom ICs  
Company: Gary Smith EDA
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One major cause of increased design costs is due to semiconductor IC scaling. Scaling no longer offers the "win-win" of past scaling increases which improved performance. Today, scaling increases power and variability in design. As noted in a recent worldwide custom IC survey of design engineer management, 37% identified variation-aware design as becoming important when designing at a 90-nm process node, but 60% saw 65nm as necessary to implement design variation and 85% saw it as required by 45nm.

Variation design is a rapidly growing factor in custom IC design. Design variation is defined as the variation in parametric results caused by process and environmental (process, voltage, temperature), random variation, and layout dependent effects (parasitics, proximity). A total of 23% of design organizations surveyed indicated they already have variation-aware design tools deployed, and another 24% intend to implement those tools in 2011. A 100% growth in organizational adoption of variation-aware design tools is expected by year-end 2011 as custom design moves to 45-nm and below process geometries.

Access the entire document on the Gary Smith EDA website.

E-mail Gary Smith EDA for more information.

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Gary Smith EDA
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Keywords: ASICs, ASIC design, custom IC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, design for yield, design-for-yield, DFY, Gary Smith EDA,
205/34332 7/22/2011 701 89
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