|Company: Cadence Design Systems, Inc.|
As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design teams are looking up 3D ICs with through-silicon vias (TSVs). 3D ICs promise "more than Moore" integration by packing a great deal of functionality into small form factors, while improving performance and reducing costs. 3D IC packages may accommodate multiple heterogeneous die — such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS) — at different process nodes, such as 28nm for high-speed logic and 130nm for analog.
This provides an alternative to system-on-chip (SoC) integration, potentially postponing an expensive move to a new process node for all of the functionality developers want to place in a single package. 3D ICs with TSVs are expected to have a broad impact in areas such as networking, graphics, mobile communications, and computing, especially for applications that require ultra-light, small, low-power devices. Specific application areas include multi-core CPUs, GPUs, packet buffers/ routers, smart phones, tablets, netbooks, cameras, DVD players, and set-top boxes. While there is great interest in this emerging technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is still in flux, and design, verification and test challenges need to be resolved.
This paper presents a brief overview of 3D IC technology, and then discusses design challenges, ecosystem requirements, and needed solutions. While various kinds of multi-die packages have been available for many years, this paper focuses on Silicon Realization of stacked die with TSVs, particularly those where different types of die are stacked (such as logic, memory, analog, digital, or RF). From a design standpoint, the good news is that extensive retooling is not needed for 3D ICs. There is no need to acquire a new "3D" design system. There are also no apparent showstoppers in process technology. However, new capabilities are needed in such areas as architectural analysis, floorplanning, place and route, thermal analysis, timing, signal integrity, IC/package co-design, and test. Some of these capabilities are available today, and others are under development.
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|Keywords: ASICs, ASIC design, custom IC design, 3D ICs, 3D chips, stacked ICs, packages, packaging, through-silicon vias, TSV, Cadence Design Systems,|
|205/34778 9/30/2011 1667 126|
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