In the age of broadband Internet, 4G smart phones, and untethered tablet computing, there is a relentless demand for ever-increasing computing performance. While processing performance has rapidly progressed, initially via increasing clock speeds and then later in the 1990’s via architectural innovations such as instruction level parallelism, pipelining and the issuing of multiple instructions per cycle, memory performance has not kept pace, creating the traditional processor memory gap. But, despite huge increases in on-chip memory capacity in an attempt to temper that gap, and the advent of multicore architectures (once again increasing the effective processing performance), SOC architects and designers are still struggling to meet the performance requirements of today’s data-hungry applications. A key reason for this remains the fundamental processor memory performance gap.