| Accurate Quantitative Physics-of-Failure Approach to Integrated Circuit Reliability |
| Source: DfR Solutions |
Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs, ADCs, and memory. They are susceptible to electrical, mechanical and thermal modes of failure like other components on a printed circuit ... read more |
| Achieving 3.2 Gb/s, 400 MTS AGTL+ IO Through Robust Power DeliveryDesign with Minimal Package Size |
| Source: Sigrity, Inc. |
This paper details the design of an optimized and robust IO power delivery network for the 400MTS (double pumped 200MHz), 3.2Gbytes/s, AGTL+ Processor-Side Bus (PSB) that links the Intel MCH chipset and the Intel Pentium 4 processor. The MCH package si ... read more |
| Achieving Design Closure with Constraint-Driven Synthesis |
| Source: Mentor Graphics Corp. |
As the use of Field Programmable Gate Arrays (FPGAs) continues to become the hardware
design engineer’s choice for implementing custom logic and Intellectual Property (IP), there is an
ever-developing need for the EDA industry to standardize on a com ... read more |
| Achieving Design Security Requirements Using eASIC’s Technology |
| Source: eASIC Corp. |
Complex digital system designs can be implemented at the high-end in full-custom application specific IC (ASIC)
or at the low end in programmable logic devices (PLD) or FPGAs. There are pros and cons for choosing each type
of device customization. Th ... read more |
| Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP |
| Source: Synopsys, Inc. |
This paper describes the main power versus resolution trade-offs existing in the design of pipeline analog-to-digital converters (ADCs). It also discusses how digital gain calibration, one of the key techniques employed, eases those trade-offs, thus ac ... read more |
| Advanced Methods for SOC Concurrent Engineering |
| Source: Mentor Graphics Corp. |
In this paper we will present how we used one part of
the system-to-RTL flow, known as "RTL Platforms," based
on HW/SW co-verification, to reduce the development
time of a complex multi-processor design. The device is a
network termination or home ... read more |
| Advanced Stimulus Generation with DesignWare Verification IP and Verification Methodology Manual for SystemVerilog |
| Source: Synopsys, Inc. |
This paper shows how to perform advanced stimulus generation using DesignWare Verification IP and VMM for SystemVerilog. It focuses on two key topics - Exceptions and Scenario Generation. Exceptions represent protocol deviations or injected errors. Alt ... read more |
| Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog |
| Source: Synopsys, Inc. |
This paper is the second in a series. It discusses the benefit of using constrained random verification and briefly recaps the Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVe ... read more |
| Advanced Virtual Platform Validation Methodology |
| Source: JEDA Technologies, Inc. |
The objective of this short summary paper is to show to ESL model and platform developers as well as system architects how to use advanced ESL model validation methodologies to increase model quality and thus reduce the time spend to development and de ... read more |
| Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions |
| Source: Posedge, Inc. |
The growth of the Internet continues to drive the need for faster network packet management and improved network security. The two must be fused together today because separation of either leads to deficiencies in both, due to the distribution and rout ... read more |
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