Cadence Design Systems enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Designers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

SOCcentral Feature Articles
A Call to Action: How 20nm Will Change IC Design	2/8/2013
TLM-Driven Design and Verification: Time for a Methodology Shift	1/7/2013
Building Energy-Efficient ICs from the Ground Up	12/5/2012
3D ICs with TSVs: Design Challenges and Requirements	12/3/2012
Solutions for Mixed-Signal SOC Implementation	10/25/2012
Solutions for Mixed-Signal SOC Verification	8/21/2012
The Evolution of Power Format Standards	7/16/2012
Mixed-Signal Design Trends and Challenges	6/1/2012
Extending the Metric-Driven Verification Methodology to TLM	3/30/2012
Streamlined Verification Plans Using the Metric Driven Verification Flow	2/23/2012
Error Checking and Functional Coverage with SystemVerilog Assertions	2/2/2007
Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort	6/26/2006
Generating Faster-than-at-Speed Delay Tests with On Product Clock Generation	5/1/2005
Evolution and Adoption of Formal Analysis	4/14/2005
Components of a Complete Assertion-Based Verification Solution	12/13/2004
Articles Online
FinFET Challenges and Solutions: Custom, Digital, and Sign-Off	4/22/2013
The Five Key Challenges of 20-nm Custom and Analog Design	4/22/2013
Building Your UVM Verification Environment for Cache-Coherent Interconnects	4/4/2013
Dynamic Partitioning Speeds Memory Characterization	3/25/2013
The Coming Impact of Mobile PCI Express (M-PCIe) on SOCs and Devices	3/12/2013
Accelerated VIP Solves Firmware and Driver Integration and Validation Trade-Offs	1/31/2013
Why USB 3.0 Will Drive SOC Verification in 2013	1/15/2013
Hybrid Execution and Software-Driven Verification Will Emerge in 2013	12/19/2012
Smashing Through the Mobile Device Memory Bottleneck	12/11/2012
Will LDE Stand Between You and Your Next Smart Device?	10/30/2012
Electrically-Aware Design Improves Analog/Mixed-Signal Productivity	10/29/2012
Understanding 28-nm SOC Design with ARM-Based Cores	10/19/2012
Multicore ARM SOCs Face Cache Coherency Dilemma	10/2/2012
How Flash and DRAM Growth Trends are Reshaping the Memory Industry	8/7/2012
Developing High-Frequency Integrated Circuits for Test and Measurement	7/19/2012
Virtual Prototyping Tools Speed Development for FPGAs with ARM-based SOC Subsystems	5/15/2012
Top 10 Tips for Success with Formal Analysis-Part 3	5/14/2012
Hierarchical Methods for Power-Intent Specification	4/30/2012
Building Predictability into Your Low-Power Design Flow	4/16/2012
Building a NAND Flash Controller with High-Level Synthesis	3/19/2012
What's the Difference Between Software Development Platforms?	3/14/2012
Wide I/O Driving 3-D with Through-Silicon Vias	2/22/2012
Top 10 Tips for Success with Formal Analysis-Part 2	1/30/2012
Combining Prototyping Solutions to Solve Hardware/ Software Integration Challenges	12/13/2011
Top 10 Tips for Success with Formal Analysis-Part 1	12/12/2011
Assertion-Based Verification in Mixed-Signal Design	10/17/2011
FPGA Functional Verification: Why Bother?	10/11/2011
Dealing with the Pains of Technology Adoption	9/26/2011
3D-IC Design: The Challenges of 2.5D versus 3D	9/14/2011
Realizing the Promise of Electrically-Aware Custom IC Design	8/9/2011
Marrying Flexibility and Complexity Verifying a DSP in an FPGA	8/4/2011
3-D IC Design: New Possibilities for the Wireless Market	6/7/2011
Achieve your SOC Design Goals: Measure Twice, Cut Once!	5/23/2011
Platforms Continuum for System Realization	5/5/2011
Using Verification Coverage with Formal Analysis	4/13/2011
EDA Tools for 3D IC Design	4/1/2011
System-Level Design: Five Likely 2011 Trends	4/1/2011
How Many-Core Will Reshape EDA	3/7/2011
Using Co-Design to Optimize System Interconnect Paths	1/16/2011
How an Emerging Methodology Better Supports SOC Design	1/11/2011
Validate Hardware/ Software for Nextgen Mobile/ Consumer Apps Using System Development Tools	12/14/2010
High-Level Synthesis: Ready for Prime Time?	11/23/2010
Metric-Driven Validation, Verification and Test of Embedded Software	11/10/2010
Reduce Embedded SOC Design Cost and Optimize IP Integration	8/16/2010
The Transformation of Silicon to System Design	6/1/2010
Using Unified Modeling Methods to Reduce Embedded Hardware/ Software Development	5/13/2010
Tackling Formal Assumptions Through Verification Planning	7/7/2009
The Need to Address Power During Manufacturing Test	10/6/2008
ESL Handoff: Closer Than You Think	7/8/2008
What Floorplan Information Is Needed for Synthesis	4/22/2008
Multi-language Functional Verification Coverage for Multi-Site Projects	4/12/2008
Open Verification Methodology: Why Now?	4/1/2008
How to Specify and Verify Power-Cycled SOCs for Checking and Coverage	3/18/2008
Multi-language Functional Verification Coverage for Multi-site Projects	2/18/2008
Simplifying PLL Design	2/12/2008
Verification Platform for Complex Designs	12/31/2007
Design with Verification: Not an Oxymoron	11/5/2007
Make Front-End Power Predictable	10/19/2007
Sign-Off for Manufacturability	10/8/2007
Making Verification Methodology and Tool Decisions	8/6/2007
Getting Back to Basics with Planning, Metrics, and Management	7/13/2007
Design Constraint Verification and Validation: A New Paradigm	6/18/2007
A Methodology for Front-End Ppower Predictability	4/18/2007
Efficient Computing and Advanced Visualization Accelerates Electronic Design	4/12/2007
Pragmatic Adoption of Formal Analysis	3/29/2007
How to Architect, Design, Implement, and Verify Low-Power Digital ICs	1/29/2007
Practical Applications of Statistical Static Timing Analysis	12/18/2006
Enterprise System Level (ESL) Verification - Part 2	12/4/2006
We Need "Enterprise" System-Level Solutions	11/20/2006
Why It's Time to Redefine ESL	11/3/2006
A Holistic Approach to System-Level Design andVverification Success	10/9/2006
Flexible Constraint-Management Drives Next-Generation Mixed-Signal Design	9/11/2006
An Overview of On-chip Compression Architectures	9/1/2006
Virtual Prototyping Speeds Mixed-Signal IC Design	8/21/2006
Verification IP Takes a Broader Role	8/7/2006
Constraint-Driven Physical Design Speeds IC Convergence	6/26/2006
Facilitating System-in-Package (SiP) Design	6/5/2006
How to Adopt Assertion-Based Verification (ABV) into Standard Design Flows	5/8/2006
Keys to Simulation Acceleration and Emulation Success	4/27/2006
Multiprocessing Speeds IC Physical Verification	9/12/2005
Designing ICs with the "X" Architecture	8/29/2005
Improving Yield in RTL-to-GDSII Flows	7/11/2005
How to Improve Verification Planning	6/27/2005
A Tale of Two Languages: SystemC and SystemVerilog	6/1/2005
Reliable Sign-off at Smaller Nodes	5/12/2005
Getting the Most Out of Formal Analysis	4/25/2005
Ensure Valid Design Constraints Throughout the Design Process	4/14/2005
Techniques for Reducing Signal-Integrity Pessimism	1/24/2005
Nanometer Yield Enhancement Begins in the Design Phase	1/20/2005
The Why, Where and What of Low-Power SoC Design	12/2/2004
Reuse of Analog Mixed Signal IP for SoC Design	11/8/2004
A Primer on Processor-based Emulation	10/21/2004
How Diagnostics Accelerate Nanometer Yield Ramp	10/1/2004
Delay Testing for Nanometer Chips	9/1/2004
Minimize IC Power without Sacrificing Performance	7/15/2004
Verifying SoCs and IP in Parallel	7/12/2004
Approaches to Accelerated HW/SW Co-Verification	6/25/2004
How Specifications Drive Analog Design	4/23/2004
Enabling Analog-IP Reuse: Relating Requirements to Reality	4/7/2004
Hearing-Aid SoC: Tiny Gear, Big Challenges	3/17/2004
A New Approach to Nanometer Delay Modeling	3/4/2004
Quality of Silicon Metric Gauges EDA Tool Success	2/12/2004
Platform-Based Design for System-on-Chip	1/22/2004
Nanometer IC Routing Requires New Approaches	12/12/2003
Methodology Enshrines IC, Package and PCB	12/8/2003
How Designers Can Increase Parametric Yield	11/21/2003
Maximize Your Utilization of Acceleration and Emulation	9/26/2003
Right on Time: Requirements for Advanced Custom Design	8/22/2003
Maximize CPU Power for Physical Verification	6/13/2003
Why You Need RTL Virtual Prototyping	3/28/2003
DFT: A Systems Technology for System Chips	3/3/2003
SystemC Verification Library Speeds Transaction-Based Verification	2/24/2003
It's About Time: Charting a Course for Unified Verification	1/28/2003
Crosstalk Glitch Analysis: How to Get it Right	1/17/2003

Tutorials, White Papers, etc.

3D ICs with TSVs: Design Challenges and Requirements

Accelerating Nanometer Yield Ramp with Yield Diagnostics

Clock Domain Crossing

Closing the Nanometer Yield Chasm

Designing Clock Signals — Predictability Counts

Down to the Wire: Requirements for Nanometer Design

It's About Time: Requirements for the Verification of Nanometer-scale ICs

Managing Signal Integrity in Nanometer Digital Designs

Modeling and Simulation of Jitter in PLL Frequency Synthesizers

Nanometer Sign-off: From Design to Manufacturing

Nanometer Test: Methodology and Economics

On Target, On Time: A Co-Design Methodology for System Interconnect

Parasitic Extraction for Deep Submicron and Ultra-deep Submicron Designs

Quality of Silicon: A Wired Way to Success

Receiver Characterization using Periodic Small-Signal Analysis

Reducing the Development Cycle for Third Generation Wireless Communications Systems with Parallel Simulations

Reducing Time to Market: Parallel Software Development with Emulation and Simulation Tools for MXC Architectures

Return on Investment: A Co-Design Methodology for System Interconnect

Right On Time: Requirements for Advanced Custom Design

Rise of D/MS Semiconductors and Systems-on-a-Chip

RTL Model Development and Functional Verification: Using the Formal Verification Technique Know as Equivalence Checking

Signal and Design Integrity

Signal Integrity Closure

Silicon Design Chain Extends Low Power Design Collaboration

Silicon Validation of Full-chip Extraction

Spec-Driven Design

Successfully Designing FPGA-Based Systems

The Advanced Custom Design Methodology

Webcasts
USB 3.0 Verification Challenges and Solutions	2/19/2013
How to Verify ARM ACE Coherent Interconnects with UVM Verification IP	11/8/2012
Functional Verification	10/16/2012
Shorter, Better and Easier PCIe and NVMe Verification Flow with Advanced Technologies	7/25/2012
How to Make Your SOC Simulation Run 100X Faster with Accelerated Verification IP	5/30/2012
Industry Leaders Unveil Shared Vision for 20nm	5/1/2012
The Verification IP Behind the Cloud Technology Revolution	4/10/2012
FPGA-Based Prototyping Is Hard to Do: Or Is It?	8/30/2011
Cadence Functional Verification	8/23/2011
Moving Up to High-Level Synthesis	12/8/2010
System-Level Simulation Acceleration with UVM/OVM	12/1/2010
Parasitic-Aware Design: A Complete Analog Design Flow	11/16/2010
Increase Your Productivity and Profitability: A Deterministic Path to Silicon Realization	11/2/2010
Best Practices and Methods for Mixed-Signal Verification	11/18/2009
Best of Breed PCI Express IP and VIP Solution for SOC Designers	2/12/2008
Manage Power at Each Design Stage with a Holistic Solution to Low-Power Design	11/6/2007
Circuit-Simulation-Driven RF/Analog System-In-Package Design	9/6/2007
Accurate Verification of Next-Generation Custom Digital SOC and Memories in 65/45-nm Technologies	6/28/2007
Verification of Next-Generation Wireless SOC and Systems in Package	6/26/2007
Verification of Next-Generation Mixed-Signal Communication SOCs	6/21/2007
Verification of Complex Analog Designs	6/19/2007

EDA Tools
Incisive Conformal ASIC	Acceleration
Incisive Unified Simulator	Acceleration
Incisive XLD	Acceleration
Incisive XLD Base	Acceleration
Incisive AMS	Analog/Mixed Signal
Dracula Verification	Circuit Simulation
Allegro Design Entry CIS 210	Design Entry
Allegro PCB Design 220	Design Entry
Allegro PCB Design 610	Design Entry
Allegro PCB Librarian	Design Entry
Virtuoso Layout Editor	Design Entry
Encounter Test Solutions	Design for Test
Allegro Design Entry HDL 610	Design Management
Cadence and TSMC Library Distribution	Design Management
Diva Physical Verification	Design Management
Encounter digital IC design platform	Design Management
Incisive Conformal Ultra	Design Management
Assura Design Rule Checker	Design Suites
Incisive Conformal Custom	Formal Verification
Incisive Conformal Equivalence Checking	Formal Verification
Fire & Ice QXC	Layout/Floorplanning
Fire & Ice QXT	Modeling/Libraries
MaskCompose	Modeling/Libraries
Allegro Package SI 620	Physical Design
Allegro PCB Router	Placement & Routing
Nano Encounter	Placement & Routing
NanoRoute Ultra	Placement & Routing
First Encounter Ultra	Prototyping/Emulation
Allegro PCB SI	Signal Integrity
CeltIC	Signal Integrity
BuildGates	Synthesis
Encounter RTL Compiler	Synthesis
Assura Layout vs. Schematic (LVS) Verifier	Verification
Incisive Verification Platform	Verification

News
TSMC Certifies Cadence Tempus Timing Sign-off Solution for 20-nm Designs	5/22/2013
Cadence Introduces the Tempus Timing Sign-off Solution	5/20/2013
Yamaha Reduces Power by 10% and Speeds Turnaround by 2X for Mobile Applications Using Cadence Virtuoso Liberate and Spectre Tools	5/13/2013
Cadence Incisive Enterprise Simulator Improves Low-Power-Verification Productivity by 30%	5/7/2013
Cadence to Acquire Evatronix's IP Business	5/7/2013
Cadence and GlobalFoundries Collaborate to Improve DFM Sign-Off for 20- and 14-nm Nodes	4/29/2013
Cadence and TSMC Strengthen Collaboration on Design Infrastructure for 16-nm FinFET Process Technology	4/8/2013
ARM and Cadence Partner to Implement First Cortex-A57 64-bit Processor on TSMC 16nm FinFET Process	4/4/2013
Cadence Announces First Commercially Available Design IP and Verification IP for Mobile PCI Express	3/11/2013
Cadence to Acquire Tensilica	3/11/2013
Cadence Rolls Out 2013 CDNLive User Conferences	2/27/2013
Cadence Expands IP Portfolio with Agreement to Acquire Cosmic Circuits	2/7/2013
Cadence and GlobalFoundries Collaborate to Enable Custom/Analog and Digital Design of 20-nm Manufacturing Process	2/5/2013
GlobalFoundries and Samsung Support New Cadence Virtuoso Advanced Node for 20-nm and 14nm Processes	2/5/2013
Cadence Releases Verification IP for USB SuperSpeed Inter-Chip Specification	1/31/2013
Cadence Unveils New Virtuoso Advanced Node for 20-nm Design	1/28/2013
Avago Technologies Improves Performance by 57% on 28-nm IC Using Cadence Encounter Digital Implementation System	1/23/2013
Imec Teams with Cadence to Present Automated Design-for-Test Solution for 3D Memory-on-Logic	1/22/2013
New Release of Cadence Incisive Platform Doubles Productivity of SOC Verification	1/22/2013
ARM and Cadence Tape Out First 14-nm FinFET Test Chip Targeting Samsung Process	12/24/2012
Cadence Announces Availability of First Design IP and Verification IP for Ethernet-Based Automotive Connectivity	11/27/2012
Cadence Synthesis Technology Speeds Time-to-Production for Renesas Micro Systems	11/26/2012
Open-Silicon Reaches 2.2-GHz Performance on 28-nm ARM Dual-Core Cortex-A9 Processor Using Cadence Encounter Technologies	11/6/2012
Cadence Announces Tape-Out of 14-nm Test-Chip with ARM Processor and IBM FinFET Process Technology	10/30/2012
Cadence SiP Technologies and Allegro Package Designer Optimized for Hand-Held Consumer Electronics Market	10/22/2012
TSMC Selects Cadence Virtuoso and Encounter Platforms for Its 20-nm Design Infrastructure	10/16/2012
ITRI Tapes Out 3D-IC Chip Using Cadence Technology	10/15/2012
TSMC Validates Cadence 3D-IC Technology for Its CoWoS Reference Flow	10/15/2012
Cadence Introduces New Verification Debugger, Offering Significant Productivity Improvements and Time Savings	10/9/2012
Cadence Sign-Off Solution Cuts Design-Cycle and Timing-Convergence Time for Complex STMicroelectronics SOC	10/9/2012
CSR Accelerates Low-Power, Mixed-Signal Chip Tape-Oout with Cadence Encounter	10/9/2012
Cadence Allegro Accelerates Product Creation Through Efficient Collaborative ECAD Environment Using Microsoft SharePoint	9/25/2012
Cadence Releases OrCAD 16.6, Boosts PSpice Performance by Up to 20%	9/25/2012
Cadence DDR4 Design IP Solutions Now Proven in 28-nm Silicon	9/4/2012
Denso Achieves Significant Productivity and Quality-of-Results Advantages with Cadence Mixed-Signal, Low-Power Solutions	8/28/2012
Cadence Publishes Comprehensive Book on Mixed-Signal Methodology	8/14/2012
ARM and Cadence Collaborate to Optimize ARM POP Solutions with Cadence Encounter Digital Platform	8/8/2012
Cadence Encounter Helps Renesas Gain Advantage in Design Power, Area and Productivity	7/18/2012
Fujitsu Semiconductor Selects Cadence Sign-Off Solution for Its Newest Reference Design Flow	7/17/2012
Sharp Achieves 2X Improvement in Turn-Around Time with Cadence Encounter RTL-to-GDSII Flow	7/17/2012
Cadence Adds New Capabilities to Its PCI Express Verification IP Including PIPE4 Support	7/11/2012
Cadence Acquires Sigrity	7/3/2012
Cadence Digital PHY Design IP Adopted by Brite Semiconductor	7/3/2012
Cadence Encounter RTL-to-GDSII Flow Provides Improved Power, Performance and Area for Ambarella	6/27/2012
Samsung and Cadence Deliver 20-nm Digital Design Methodology	6/5/2012
Cadence Collaborates with TSMC on 3D-IC Design Infrastructure	6/4/2012
Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20-nm Phase I Certification	6/4/2012
Cadence Physical Verification System Qualified for TSMC 28-nm and 20-nm Processes	6/4/2012
STMicroelectronics Tapes Out 20-nm Test Chip Using Cadence Tools	5/31/2012
Cadence Announces Updated Design and Verification IP for DDR PHY Interface	5/29/2012
Carbon Design Systems and Cadence Partner for IP Optimization	5/24/2012
Nufront's Third-Generation Mobile Applications Processor Powered by Cadence DDR3/ 3L/ LPDDR2 Memory-Interface IP Solution	5/21/2012
Altis Semiconductor Releases Enhanced Versions of PDKs for 130-nm Processes Based on Cadence Virtuoso OpenAccess Platform	5/15/2012
Cadence Expands System and SOC Verification Offerings	5/15/2012
Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications	5/15/2012
Netronome Acieves Power, Performance and Area Benefits with Cadence Encounter Technology	5/14/2012
TowerJazz Introduces Reference Flow 2.0, Featuring Key Cadence Technology, for Its Power-Management Platform	5/14/2012
Fujitsu Semiconductor Adopts Cadence Chip-Planning System for MCU Chips	5/8/2012
Cadence Announces TripleCheck IP Validator for Faster IP Compliance Testing	5/1/2012
Cadence OrCAD Capture Marketplace Now Available on Desktop Browsers	5/1/2012
Cadence Connects and Inspires EDA Industry at Its CDNLive!	4/24/2012
Cadence Low-Power, Advanced-Node Digital Technology Incorporated into SMIC 40-nm Reference Flow	4/10/2012
Breker Verification Systems Joins Cadence Connections Program	4/9/2012
Cadence Announces Support for New Interface Verification IP for Development of Cloud Infrastructure	3/27/2012
Cadence Delivers High-Performance, Low-Power Design IP Supporting LPDDR3 Memory Standard	3/21/2012
Cadence Board Member Alberto Sangiovanni-Vincentelli Honored with EDAA Lifetime Achievement Award	3/16/2012
Vivante and Cadence Unveil Mass-Market GPU-Optimized DDR Memory Solution	3/14/2012
Cadence Offers IC Design Program for Start-Ups in Australia	3/6/2012
Cadence Accelerates High-Performance, Giga-Scale, 20-nm Design with Next-Generation Encounter RTL-to-GDSII Flow	3/5/2012
Real Intent Joins Cadence Connections Program	2/28/2012
Cadence Expands Proven Ethernet IP Offering with 40/100 Gigabit Ethernet Solution	2/21/2012
Cadence Collaborates with Samsung Foundry to Deliver DFM Solution for 32-, 28- and 20-nm Chip Design	2/6/2012
Cadence Publishes Book on Advanced Verification Methodologies	1/17/2012
Cadence Expands Proven NAND Flash Design IP Offering with ONFI 3 PHY and Controller	1/9/2012
Cadence Palladium XP Verification Platform Speeds Deployment of Panasonic SOCs for Digital Consumer Products	12/13/2011
Cadence Wins TSMC EDA Partner Award for 3D-IC Technology	11/15/2011
TowerJazz Reference Design Flow 2.0 Fully Qualifies Cadence Mixed-Signal Solution and Process Design Kit	11/3/2011
Cadence Palladium XP Enables QLogic to Rapidly Develop Sophisticated Network Switch	10/31/2011
Samsung and Cadence Announce Production of Breakthrough 32nm HD Digital Camera SOC for Ambarella	10/27/2011
Xilinx and Cadence Introduce an Extensible Virtual Platform to Enable Software-Centric Approach for Embedded Software Developers	10/27/2011
Atrenta Joins Cadence System Realization Alliance	10/24/2011
ARM and Cadence Achieve Milestone with Tape-Out of 20-nm ARM Cortex-A15 MPCore Processor	10/18/2011
Cadence Issues Call for Papers for the 2012 CDNLive! Silicon Valley Users Conference	10/17/2011
Cadence Library Characterization Scripts Now Available in New TSMC Reference Kit	10/17/2011
Fuji Electric Cuts Development Time 25% with Cadence Virtuoso Accelerated Parallel Simulator	10/5/2011
X-FAB Qualifies Cadence Physical Verification System for All Process Nodes	10/5/2011
Cadence Enables ST-Ericsson to Achieve Significant Productivity Gain for Its 40-nm Baseband Chip Design	9/27/2011
Cadence Accelerates Adoption of Emerging Mobile Standards with Expanded Verification IP Portfolio	9/26/2011
Altis Semiconductor Standardizes on Cadence MaskCompose Reticle and Wafer Synthesis Suite	9/21/2011
Giantec Semiconductor Moves to Cadence Technology	9/21/2011
Cadence and Dassault Systemes Expand Relationship for Greater Control and Management of Semiconductor Design Data	9/20/2011
Cadence Announces DFI 3.0-Compliant Design and Verification IP	9/20/2011
Fujitsu Standardizes on Cadence DFM Technologies for 28-nm ASIC and Mixed-Signal Designs	9/20/2011
Cadence and GlobalFoundries Speed DFM Sign-Off at 32 and 28nm	8/30/2011
Sunplus Technology Picks Cadence TLM Flow for Next-Generation Multimedia ICs	8/8/2011
HiSilicon Boosts Productivity Deploying Advanced Cadence Simulator	7/18/2011
Cadence Acquires Azuro	7/12/2011
Cadence Encounter Digital Flow Instrumental in Tape-Out of Samsung 20-nm Test Chip	7/11/2011
HDL Design House Joins Cadence IP Alliance Program	7/4/2011
Cadence Donates UVM World Website to Accellera	6/29/2011
Cadence Accelerates Development of Multiprocessor Mobile Devices with New ARM ACE Verification IP	6/7/2011
Cadence Collaborates with TSMC on New 28-nm Flows	6/7/2011
Cadence Extends IP Offering; Collaborates with TSMC via Open Innovation Platform	6/7/2011
Duolog Collaborates with Cadence to Enable Faster System Realization	6/7/2011
imec and Cadence Deliver Automated Solution for Testing 3D Stacked ICs	6/7/2011
Lorentz Solution Collaborates with Cadence to Enhance RFIC Design Solutions	6/2/2011
Cadence to Unveil OrCAD Capture Marketplace with Industry-First Online Apps	5/11/2011
Cadence Acquires Altos Design Automation	5/10/2011
Cadence and TSMC Collaborate to Deliver DFM Services for TSMC Advanced Processes	5/9/2011
Cadence Announces Suite Approach that Bridges Hardware and Software to Reduce System Integration Time	5/5/2011
Bosch Deploys Cadence Unified Custom/ Analog Flow to Gain Overall Design Productivity	5/2/2011
New Cadence Allegro Technology Boosts Productivity and Predictability for Silicon, SOC and System Developers	4/25/2011
EMA and Cadence Extend Channel Partnership to Sell Complete Line of PCB Design Tools	4/13/2011
Cadence Announces Availability of DDR4 IP Solution	4/11/2011
Cadence Releases Wide-I/O Memory Controller IP Solution	3/28/2011
CERN Relies on Cadence Services to Provide an Advanced and Integrated Design Environment	3/22/2011
Cadence Enhances Unified Custom/ Analog Flow to Boost Productivity at Nodes Down to 20nm	3/14/2011
Cadence Opens and Extends Verification IP Catalog for Use Across Silicon, SOC and System Development	2/28/2011
Duolog Extends Solutions to Support EDA360 Vision in Collaboration with Cadence	2/24/2011
IMS CHIPS Standardizes on Cadence Silicon Realization Product Line for Advanced Gate Array Design	2/23/2011
Broadcom Expands Use of Cadence Verification Computing Platform	2/22/2011
Cadence Announces Global Series of Seminars on Mixed-Signal Design	2/3/2011
STARC and Cadence Develop In-Design DFM for 32/28-nm Silicon Realization	1/24/2011
Spreadtrum Standardizes on Cadence Design Flow for Its First 40-nm Product	1/21/2011
Cadence Introduces 32/28-nm Low-Power RTL-to-GDSII Silicon Realization Reference Flow for Common Platform Alliance	1/17/2011
Cadence Boosts Verification Productivity for Complex FPGA and ASIC Design	1/10/2011
Cadence C-to-Silicon Compiler Supported in Fujitsu Semiconductor's ASIC Flow for System Realization	12/9/2010
SMIC Adopts Cadence DFM and Low-Power Silicon Realization Technology for 65-nm Reference Flow	12/9/2010
TowerJazz Announces Cadence Reference Flow 1.0 for Analog/ Mixed-Signal 180-nm Power-Management Process	12/2/2010
CST Announces Joint Marketing Agreement with Cadence Design Systems	12/1/2010
Open-Silicon Achieves Ultra High Performance Using Cadence Silicon Realization Technology to Tape-Out 2.4-GHz ASIC Processor	11/15/2010
Cadence Unveils Holistic Approach to Silicon Realization	10/27/2010
Cadence and Xilinx Introduce FPGA IP Ecosystem Microsite	10/20/2010
Verific Joins Cadence Connections Program	10/20/2010
Sunplus Reduces Design Cycle On High-Speed, Multi-Million-Gate SOC Using Cadence Encounter Digital Implementation System	9/30/2010
Cadence Offers Optimized Implementation Methodology for Silicon Realization of New ARM Cortex-A15 MPCore Processor	9/28/2010
SMIC Adopts Cadence Silicon Realization End-to-End Product Line for 65 to 40-nm Design	9/21/2010
Global Unichip Boosts Design Productivity With Cadence Encounter Timing System	9/14/2010
Andes Technology Adopts Cadence Digital Front-End Low-Power Flow	9/1/2010
Cadence Aligns Workforce to Deliver On EDA360 Vision	8/5/2010
Fujitsu Adopts Cadence Encounter Conformal ECO Designer	7/22/2010
Cadence and ARM Collaborate to Create ARM-Optimized System Realization Solution	7/21/2010
Cadence Develops Die Model Enabling Comprehensive Chip-Package Co-Design Solution with Fujitsu	7/20/2010
Fujitsu Adopts Cadence Chip-Planning Technology	7/20/2010
Hitachi Achieves 10,000X Performance Boost Using Cadence Technology to Verify Complex Design	7/19/2010
Hitachi Raises System-Level Simulation Performance 100X with Cadence Palladium Transaction-Based Acceleration	7/19/2010
Cadence QRC Extraction Adopted by STMicroelectronics for 40-nm Analog/ Mixed-Signal Design	7/16/2010
Casio Cuts Design Cycle Time and Improves Quality Using Cadence Front-End Technologies	7/16/2010
SiS Adopts Cadence Technologies for Advanced SOC Designs	6/30/2010
Cadence Completes Acquisition of Denali	6/21/2010
Cadence Delivers Extensive Support for TSMC AMS Reference Flow 1.0 for 28-nm Process	6/14/2010
Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0	6/14/2010
Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World	6/14/2010
Cadence Announces Comprehensive SOI Design Hub	6/11/2010
Cadence and IBM Team to Develop Leading-Edge IP	5/24/2010
Rapid Bridge LiquidIP Now Available as Part of Cadence Open Integration Platform	5/24/2010
Computer Simulation Technology Announces Closer Cooperation with Cadence	5/20/2010
Cadence to Acquire Denali	5/14/2010
Cadence Accelerates SOC Realization, Reduces Costs with New Open Integration Platform	5/7/2010
VIA's Centaur Achieves Significant Benefits Using Cadence Virtuoso Space-Based Router at 65nm	5/3/2010
Cadence Debuts Verification Computing Platform	4/26/2010
Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chips	4/21/2010
HiSilicon Adopts Cadence Mixed-Signal and Low-Power Technologies	4/14/2010
LSI Adopts Broad Range of Cadence Mixed-Signal Technologies	4/14/2010
TSMC Expands Cadence Tool Support In Integrated Sign-Off Flow By Adding Synthesis, Place and Route, and RC Extraction	4/14/2010
Cadence Teams with AcAe to Accelerate Transition to Allegro PCB Products	3/29/2010
Renesas Cuts Design Time by Half on Large-Scale Consumer SOC by Using Cadence Encounter Technology	3/24/2010
austriamicrosystems Expands Reliance on Cadence Technology to Achieve Seamless Mixed-Signal SOC Designs	2/2/2010
Cadence EDI System 9.1 Addresses Productivity Crisis for Complex SOC Design	2/2/2010
Cadence Software Validated on STARC QA Database	2/1/2010
Renesas Adopts Cadence Virtuoso Technology for Mixed-Signal and Analog Design	1/27/2010
Cadence OVM SystemVerilog Solution Enables More Thorough Verification at Mitsubishi Electric	1/25/2010
NEC Electronics Adopts Cadence Encounter Digital Implementation System for 40-nm ASIC Designs	1/25/2010
Fairchild Semiconductor Selects Cadence as Primary EDA Partner	12/14/2009
Zoran Deploys Cadence Virtuoso Software for Complex, Advanced-Technology, Mixed-Signal Chip	12/14/2009
Cosmic Circuits Adopts Cadence Virtuoso 6.1 for Complex Analog and Mixed-Signal Designs	12/11/2009
AppliedMicro Standardizes on Cadence Encounter Digital Implementation System	12/10/2009
Cadence Strengthens Virtuoso Custom IC Design	12/8/2009
IC Plus Standardizes Verification Process with Cadence Incisive Solution	11/27/2009
Cadence Announces Expanded SOC Design Alliance with Toshiba	11/16/2009
Exar Selects Cadence as Mixed-Signal EDA Provider	11/5/2009
Hitachi Achieves Test Compression Levels Well Ahead of ITRS Roadmap by Leveraging Cadence OPMISR Compression Technology	11/2/2009
Arasan and Cadence Collaborate to Extend Verification Best Practices	10/29/2009
SMIC and Cadence Announce Availability of 65-nm Low-Power Reference Flow 4.0	10/29/2009
Cadence New Miniaturization Capabilities Boost PCB Designer Productivity	10/28/2009
New Cadence Allegro SiP and IC Packaging Software Facilitates Direct Input from IC Package Designers	10/28/2009
Silicon Hive Utilizes Cadence Palladium III Solution for Highest Quality IP for Multi-Core, Multi-Million Gate Designs	10/28/2009
Cadence and ARM Collaborate to Increase Engineer Productivity and Drive Down Time-to-Market for SOC Integration	10/20/2009
SMIC Adopts Cadence DFM Solutions for 65- and 45-nm IP Library Development and Full Chip Production	10/19/2009
STARC and Cadence Collaborate to Develop Next-Generation Analog/ Mixed-Signal Reference Flow	10/19/2009
Cadence Incisive Verification Management Solution Adopted By Fujitsu Microelectronics Solutions	10/14/2009
SHHIC Adopts Cadence Solutions for Advanced Semiconductor Design	10/14/2009
Cadence Extends Its TLM-Driven Design and Verification Solution to Support Leading Embedded Software Environments	10/7/2009
Cadence Enables Early Validation of Next-Gen 4G/LTE Wireless Designs with Rohde & Schwarz T&M Solution	10/5/2009
Cadence Introduces Incisive Enterprise Verifier, Delivering Dual Power of Formal Analysis and Simulation Engines	10/5/2009
Cadence Expands Multi-Core Support	10/1/2009
Cadence Physical Verification System Supports TSMC's Interoperable iDRC and iLVS Formats for 40-nm Design	10/1/2009
Linear Technology Adopts Broad Range of Cadence Mixed-Signal Design Technology	9/23/2009
X-FAB Announces New Process Design Kits for Cadence Virtuoso IC 6.1 Custom Design Platform	9/22/2009
Cadence and Global Foundries Announce Broad, Multi-Year Technology Agreement	9/1/2009
Tilera Adopts Broad Range of Cadence Solutions for Multicore Processor Design	8/26/2009
Cadence Low-Power Solution Selected for Global Unichip's PowerMagic Low-Power Design Methodology	8/17/2009
Nethra Uses Cadence Incisive Palladium to Speed Development of Advanced HD Image Processor	8/3/2009
Cadence Achieves First-Silicon Results on 32-nm Common Platform Technology	7/31/2009
Freescale Achieves Design Cycle Reduction and Superior Silicon Predictability with Cadence Model-Based Physical and Electrical DFM Solutions	7/31/2009
STMicroelectronics Adopts Cadence Encounter Signoff Solutions for Designs from 65 to 32nm	7/31/2009
Taiwan's ITRI Adopts Cadence C-to-Silicon Compiler to Boost Designer Productivity	7/31/2009
VeriSilicon Delivers Chip Designs on Time and at Lower Cost with Cadence InCyte Chip Estimator	7/31/2009
UMC Adopts Cadence 40-nm Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design	7/30/2009
Cadence Validates ARM Optimized Libraries for 45-nm SOI Process	7/29/2009
LG Electronics Adopts Cadence Conformal Technology	7/29/2009
Cadence Delivers 28-Nanometer Design Capabilities to TSMC Reference Flow 10.0	7/28/2009
TSMC and Cadence Expand Collaboration to Deliver Advanced, Feature-Rich Process Design Kits	7/27/2009
Cadence Introduces TLM-Driven Design and Verification Solution	7/16/2009
National Semi Adopts Cadence Virtuoso Simulation Solution for Complex Analog Designs	7/16/2009
Hitachi Implements 50-Million Gate Design Using Cadence Encounter Digital Implementation System	7/14/2009
Toshiba Information Systems Selects Cadence Mixed-Signal Design Solution	7/14/2009
STARC Integrates Cadence Encounter Solution for Complex, Large-Scale Designs	7/9/2009
STARC Integrates Litho-Aware 45-nm Design Flow Using Cadence Encounter	7/9/2009
Fujitsu Microelectronics Solutions Adopts Cadence Verification Technology for Toughest Mixed-Signal Designs	7/8/2009
Japan Aerospace Exploration Agency Adopts Cadence Virtuoso IC 6.1 and Spectre Simulator	7/8/2009
Hitachi Achieves 40% Reduction in PCB Place-and-Route Design Time with Cadence Global Route Environment	7/1/2009
Cadence Collaborates with Toshiba on Integrated Design Environment for COT and SOC Design	6/29/2009
Cadence and Xilinx Simplify SOC Development with Enterprise Verification Capabilities for FPGA Targeted Design Platforms	6/25/2009
Kaben Wireless Silicon Achieves Up to 7X Performance Boost with Cadence Virtuoso Accelerated Parallel Simulator	6/17/2009
Taiwan's ITRI Achieves Digital Video Tuner Tapeout Success with Cadence Virtuoso IC 6.1	6/16/2009
Cadence Announces Restructuring	6/12/2009
Cadence QRC Full Chip Extractor Qualified for TSMC's Interoperable (iRCX) Format for 65- and 40-nm Design	6/10/2009
Faraday Technology Reduces IC Power Consumption and Cuts Design Time Using Cadence Low-Power Solution	6/10/2009
Cadence Unveils Integrated Chip Planning and Implementation Solution to Improve Predictability and Reduce Risk of IC Designs	6/8/2009
Casio Selects Cadence C-to-Silicon Compiler for High-Level Synthesis	6/8/2009
China's Academy of Sciences Adopts Cadence Incisive Xtreme III to Validate Next-Generation Multi-Core Processor Designs	6/2/2009
Netronome Adopts Broad Scope of Cadence Technology	5/28/2009
Cadence Introduces FPGA-PCB Co-Design Solution	5/21/2009
Cadence Speeds Systems Development with Automated Transaction-Level Verification	5/21/2009
NXP Semiconductors Accelerates Design Cycle for 45-nm Digital TV Processor Using New Cadence Encounter	5/18/2009
PLDA Achieves IP Success with Cadence SuperSpeed USB Verification IP	5/18/2009
BroadLight Increases Network Processor Frequency by 30% Using New Cadence Encounter	5/15/2009
Sanyo Adopts Two Key Products from Cadence to Tackle Complex Analog and Mixed-Signal Designs	5/15/2009
DiBcom Leverages Combined Cadence Low-Power and Mixed-Signal Solutions to Create Advanced Mobile TV System-on-Chip	5/13/2009
Cadence Encounter Digital Implementation System Used by Gennum's Snowbush IP Group for 45-nm USB 3.0 PHY IP	5/7/2009
Jazz Semiconductor Announces Cadence Virtuoso IC 6.1 Platform Techtorial	5/7/2009
Cadence and TSMC Introduce Mixed-Signal/ RF Reference Design Kit in 65-nm Process Technology	4/23/2009
Global Unichip Announces Greater Than 3X Schedule Reduction of Full-Chip Design Closure Using Cadence Encounter Tools	4/3/2009
Cadence and NEC Electronics Announce Encounter to Support NEC Electronics' System LSI with Built-In V850 CPU Core	4/1/2009
Cadence Launches "Industry Insights" Design Community Blog	4/1/2009
Sequans Uses Cadence Low-Power Solution for Faster Tapeout of 65-nm Mobile WiMAX Single-Die Baseband Chip	3/25/2009
Cadence Enhances Low-Power Solution Enabling More Predictable Power-Efficient Design	3/17/2009
AMD Selects Cadence Incisive Palladium Series to Verify Complex Graphics Design	2/26/2009
Cadence Extends the Open Verification Methodology to Include SystemC and e Language Support	2/23/2009
Cadence Incisive Verification IP Portfolio Delivers "All-in-One" Flexibility for SOC Developers	2/23/2009
Adaptive Chips Adopts Cadence Incisive Verification Solution with the Open Verification Methodology	2/12/2009
STMicroelectronics Uses New Cadence Encounter Digital Implementation System for 40- and 32-nm Flows	1/23/2009
Cadence Expands C-to-Silicon Compiler with High-Level Synthesis Support for Altera and Xilinx FPGAs	1/21/2009
Freescale Japan Adopts Cadence Low-Power Solution for Advanced Power-Management Chip	1/21/2009
STARC Qualifies Cadence Encounter Conformal Constraint Designer for STARCAD-CEL Flow	1/19/2009
Arasan Chip Systems Debuts Mobile Eco-System with Cadence	1/14/2009
Cadence Low-Power Solution Enables Fujitsu Microelectronics Tapeout of 65-nm WiMAX Design	1/12/2009
Cadence Unveils Next-Generation Parallel Circuit Simulator for the Verification of Complex Analog and Mixed-Signal IC Designs	12/11/2008
Cadence Introduces Family of MIPI Standard-Compliant OVM Multi-Language Verification IP	12/5/2008
Cadence Provides Open Source OVM Adoption Solution for VMM Users in Response to Industry Demand	12/5/2008
Cadence Announces Encounter Digital Implementation System with End-to-End Parallel Processing Flow	12/4/2008
Cadence Announces Development of OVM Verification IP for USB 3.0 and PCI Express 3.0	11/17/2008
Cadence Launches ActiveParts Portal and Brings New Productivity-Boosting Technology to Latest OrCAD Release	11/13/2008
Cadence Restructures, Cuts 625 and More	11/6/2008
Cadence Expands Portfolio of System-Level Verification IP and SpeedBridge Adapters	11/5/2008
Cadence Encounter Test Helps Hitachi Improve Product Quality and Lower Manufacturing Test Cost	10/30/2008
Moai Electronics Accelerates Flash Memory Controller Tapeout with Cadence Logic Synthesis and DFT Solutions	10/30/2008
Cadence Low-Power Solution Enables Legend Silicon to Achieve 90-nm First Silicon Success	10/28/2008
Cadence Helps Staccato Launch Ripcord2 Single-Chip, Ultra-Wideband IC Family	10/21/2008
Cadence Expands Enterprise Verification IP Portfolio by 5X to Provide Industry's Broadest OVM Multi-Language Offering	10/16/2008
Cadence Custom Lithography Technology Addresses 22-nm Semiconductor Manufacturing	10/8/2008
Cadence, ARM Collaborate to Deliver Hardware/Software Emulation Environment	10/8/2008
OKI Network LSI Reduces Test Time 90% by Combining OVM and Cadence Incisive Technologies	9/26/2008
Cadence Works with SMIC to Deliver Virtuoso IC 6.1-Enabled Mixed-Signal Reference Flow and Process Design Kit	9/24/2008
Cadence Virtuoso Platform Enables Custom IC Designers to Achieve Breakthrough Results	9/22/2008
Cambridge Analog Technologies Deploys Cadence Virtuoso IC 6.1.3 for Faster Tapeout of Low-Power Mixed-Signal Chip	9/22/2008
New Release of the OVM Takes Verification to the Next Level	9/12/2008
Cadence Expands Enterprise Verification Solution to Include Planning, Unified Verification Metrics and Industry Databases	9/10/2008
Cadence Introduces SaaS Solutions for Semiconductor Design	9/10/2008
Tensilica Collaborates with Cadence to Create CPF-Enabled Flow for Tensilica's Multimedia Subsystems	9/10/2008
Cadence Encounter Power System Delivers Next-Generation Power Integrity and Sign-off Analysis	9/9/2008
Cadence Strengthens Low-Power Position with Early Dynamic Power Analysis and Pre-RTL Exploration	9/9/2008
Jazz Semiconductor Expands Analog-Intensive Mixed-Signal Functionality with Adoption of Cadence Virtuoso IC 6.1 Custom Design Platform	9/9/2008
Ubicom Achieves First-Silicon Success Using Cadence Encounter Timing System for StreamEngine 7000 Processor Tapeout	9/9/2008
MuChip Adopts Cadence Virtuoso Solution to Speed Wireless RF SOC Design Development	9/4/2008
SandLinks Achieves First-Time Right Silicon Using CPF-Enabled Cadence Low-Power Solution	8/26/2008
Cosmic Circuits Experiences 8X Performance Gains by Adopting Cadence Virtuoso Spectre with Turbo Technology	8/22/2008
Cadence Introduces Constraint-Driven High-Density-Interconnect Design Flow for PCBs	8/19/2008
Cadence Withdraws Proposal to Acquire Mentor Graphics	8/15/2008
Open Verification Methodology Helps KPIT Cummins Boost Productivity, Shorten Turn-Around Time	8/1/2008
OKI Turns to Cadence and the Open Verification Methodology to Speed Product Development	7/31/2008
Ricoh Adopts Cadence Encounter Platform for Digital IC Design	7/16/2008
Ricoh Adopts Cadence Virtuoso Platform for Advanced Custom IC Design Flow	7/16/2008
Cadence Expands System-Level Offerings with C-to-Silicon Compiler	7/14/2008
Calypto's Sequential Equivalence Checking Product Supports New Cadence C-to-Silicon Compiler	7/14/2008
Renesas Adopts Cadence Virtuoso Spectre Circuit Simulator with Turbo Technology	7/11/2008
Cadence Virtuoso IC 6.1 Deployed by Matsushita for Analog and Mixed-Signal SOC Designs	7/9/2008
Cadence Enhances RF Verification with High-Performance Turbo Technology and Comprehensive EM Analysis	6/17/2008
Cadence Offers to Acquire Mentor Graphics for $1.6 Billion	6/17/2008
Cadence Virtuoso Spectre with Turbo Technology Adopted by National Semiconductor	6/17/2008
Mentor Graphics Responds to Proposal from Cadence Design Systems	6/17/2008
ASSET InterTech Works with Cadence to Drive Embedded Instrumentation for Deep Analysis of Complex ICs	6/11/2008
Cadence Collaborates with Common Platform and Arm to Deliver 45-NM RTL-to-GDSII Reference Flow	6/11/2008
Cadence Collaborates with UMC to Deliver 65NM CPF-Based Low-Power Reference Design Flow	6/11/2008
Cadence Delivers Advanced DFM Solutions, Statistical Analysis and Low-Power Design Technology for TSMC Reference Flow 9.0	6/11/2008
Cadence Delivers OVM-Compliant Verification IP	6/11/2008
Renesas Adopts Cadence SoC Encounter for Large Scale Complex Chips and Flip-Chip Design	5/12/2008
Socle Technology Adopts Cadence Low-Power Solution to Address 65-nm Power Efficiency Challenges	5/12/2008
Cadence Delivers Silicon-Ready Reference Methodologies for ARM Cortex-A9 Processor	4/30/2008
Cadence Strengthens Advanced Node Design Solutions with Enhancements for Custom IC Design	4/29/2008
New Cadence Technology Speeds Analog and Mixed-Signal Verification	4/29/2008
Cadence Partners with Brazilian Government to Open Brazil's First IC Design Training Center	4/28/2008
IDT Uses Cadence Encounter Conformal Constraint Designer to Accelerate Time-to-Market	4/16/2008
Key RF Technologies from Cadence Qualified for TSMC 65-nm Node	4/16/2008
Cadence Launches Worldwide Series of User Conferences in 2008 with CDNLive! EMEA	4/10/2008
Seiko NPC Boosts Productivity in DFT Design Flow with Integrated Cadence Test and Synthesis Technologies	4/7/2008
STARC Adopts Cadence Encounter Timing System for Static Timing Analysis Signoff	4/7/2008
PLX Technology Adopts Cadence Incisive Palladium II Accelerator/ Emulator for Full System Verification	4/3/2008
Cadence Encounter Conformal ECO Designer Improves Logic Designers' Productivity	3/25/2008
Power Forward Initiative Releases Low-Power Design Methodology Guide	3/17/2008
Cadence Acquires Chip Estimate	3/12/2008
Accent Uses Cadence Low-Power Solution for Fast, Accurate Tapeout of Low-Power Production Design	2/20/2008
Cadence and Mentor Enhance Open Verification Methodology	2/14/2008
Cadence Enables STMicroelectronics to Verify Latest Multimedia Designs for Wireless Devices	2/6/2008
Toshiba Collaborates with Cadence to Improve Analog and Mixed-Signal Design Reliability at 65nm and Below	1/22/2008
Cadence and ARM Deliver Reference Methodologies for Multicore and Low-Power Devices	12/5/2007
Cadence Joins the HyperTransport Consortium	12/5/2007
Cadence Boosts Engineers Productivity with Advances in Enterprise Verification Offering	12/3/2007
Global Unichip Joins Power Forward Initiative	12/3/2007
UMC Foundry Design Kit for New Cadence Virtuoso Platform Speeds Production of 65-nm Designs	12/3/2007
Micronas Selects Cadence Incisive Plan-to-Closure Methodology for Verification Planning	11/28/2007
Cadence Expands in Russia	11/27/2007
Cadence Announces New RF Technology to Ease Design of Nanometer Wireless Chips	11/12/2007
SMIC Offers CPF-Based Cadence Low-Power Digital Reference Flow	10/24/2007
Cadence Encounter Test Helps IBM Deliver High-Volume Chips	10/23/2007
Cadence Becomes Primary EDA Supplier to NXP	10/22/2007
SMIC Offers CPF-Based Cadence Low-Power Digital Reference Flow	10/22/2007
Cadence Announces Academic Network to Promote Electronic Design Competency in Europe	10/17/2007
Anchor Bay Adopts Cadence Incisive XTREME III System for Verification of HDTV and Digital Video Products	10/15/2007
Altos and Cadence Jointly Qualify Statistical Timing Models for 45- and 65-nm Processes	10/1/2007
Renesas Electronics Adopts Cadence Statistical Timing for 45nm	9/25/2007
Cadence Expands Research Laboratory	9/24/2007
NEC Electronics America Uses Cadence Encounter for High-Performance, Low-Power ARM11 Processor	9/24/2007
RFIC Solutions Achieves 2X Increase in Productivity with Cadence Virtuoso Platform	9/18/2007
ARC and Cadence Offer New Low-Power Design Methodology for Demanding Mobile Applications	9/10/2007
Cadence Accelerates Time-to-Volume for Advanced ICs with Model-Based, Variation-Aware Design Technologies	9/10/2007
Stratosphere and Cadence Collaborate to Drive 45 Nanometer Design Yield and Performance Higher	9/10/2007
Rambus and Cadence Collaborate on PCI Express Solutions	9/4/2007
Cadence Selects Chipidea's USB 2.0 IP for Its SoC Functional Verification Kit	8/27/2007
Cadence Selects Wipro-Newlogic's Wireless LAN IP for Its SoC Functional Verification Kit	8/27/2007
New Kit from Cadence Cuts Risk and Time for Adopting Functional Verification Methodology	8/27/2007
Cadence Extends DFM Solution with Acquisition of Clear Shape Technologies	8/20/2007
Cadence and Mentor Graphics to Standardize on Open SystemVerilog Verification Methodology	8/16/2007
Cadence and SMIC Collaboration Validates RF Design Kit for Wireless IC Design	8/2/2007
Faraday Adopts Cadence Connectivity-Driven SiP Co-Design Capabilities	7/30/2007
Winbond Israel Chooses Cadence Incisive Palladium Series to Ease Design Verification	7/30/2007
Siemens IT Solutions and Services Adopts Cadence's Assertion-Based VIP	7/25/2007
Jazz Semiconductor Teams with Cadence on Support for Cadence RF and AMS Design Kits	7/23/2007
Solido Integrates New Transistor-Level Statistical Design and Verification Technology with Cadence Virtuoso and Spectre Tools	7/18/2007
Toumaz Technology Achieves First Silicon Success with Cadence Virtuoso Multi-Mode Simulation	7/18/2007
Cadence Strengthens DFM Core Technology and Solutions Through Acquisition of Invarium	7/12/2007
Cadence Extends Integrated SiP Technologies Into the Latest Custom and Digital Design Flows	7/11/2007
Cadence Works with STARC to Address 65-nm DFM Challenges	7/10/2007
Cadence Logic Design Team Solution Answers Logical-Physical Closure Conundrum	7/9/2007
Ikanos Communications Chooses Cadence Incisive Palladium Series	7/9/2007
OCP-IP Announces Support for Cadence's Assertion Based OCP Protocol Verification IP	7/9/2007
Atheros Tapes Out High Performance 802.11n Solution with Cadence Encounter Timing System and Encounter RTL Compiler	6/26/2007
TSMC and Cadence Collaborate on 65-nm Design Flow for Wireless Designs	6/26/2007
SensorDynamics Delivers First-Time-Right Silicon with Virtuoso Platform and Incisive Enterprise Specman Technologies	6/19/2007
Tensilica Enhances Reference Flow with Cadence Encounter RTL Compiler	6/19/2007
AMI Semiconductor Successfully Tapes Out Design Using Conformal Constraint Designer for Signoff	6/11/2007
Cadence QRC Extraction Tool Qualifies on TSMC's 45-nm Process Technology	6/5/2007
Realtek Achieves Low-Power Functional Closure Using Cadence Logic Design Team Solution	6/5/2007
Cadence Speeds RF Printed-Circuit-Board Design Cycle with New Allegro PCB Technology	6/4/2007
Cadence and Denali Team to Enable Advanced DDR-PHY Methodology	5/31/2007
Cadence Improves Logic Designer Productivity through Enhanced Design with Verification Flow	5/29/2007
Micrologic Design Automation Joins Cadence Connections Program	5/22/2007
STARC to Develop Low-Power Pride Reference Flow Using Common Power Format	5/21/2007
Cadence Boosts Productivity for Next-Generation PCB Design with New Allegro Platform	5/15/2007
Cadence Introduces Complete Custom IC Simulation and Verification Solution	5/15/2007
Cadence Selects Wipro-NewLogic's Wireless LAN IP for Low-Power Methodology Kit	5/15/2007
Cadence Speeds Adoption of Wireless and Consumer Low-Power Designs with Low-Power Methodology Kit	5/14/2007
Cadence Extends Verification Resources with New Plan-to-Closure Methodology Qualified Program	5/9/2007
Optichron Tapes Out Breakthrough DSP Device Using Cadence Encounter Timing System	5/8/2007
Cadence Accelerates 45-nm Design with TSMC Reference Flow 8.0	5/4/2007
Cadence Encounter and SiP Design Technologies Used by STMicroelectronics to Implement 65-nm Dual High-Definition MPEG-4 Decoder	4/30/2007
Unisys Improves Logic Design Team Productivity with Cadence Incisive Formal Verifier	4/30/2007
Cadence VoltageStorm Enables ITRI and Ambarella to Deliver Low-Power Consumer Electronics	4/24/2007
Cadence Collaborates with IBM, Samsung and Chartered to Deliver 65-nm Reference Flow	4/23/2007
Cadence Encounter Platform Delivers Leading Low-Power and DFM Features for 65-nm Design	4/23/2007
ASE Chooses Cadence for SiP Design Worldwide	4/17/2007
UMC Joins Power Forward Initiative	4/17/2007
ClearSpeed Adopts Cadence Incisive Enterprise Manager to Verify High-Performance, Low-Power Coprocessors	4/9/2007
EdXact Jjoins Cadence’s Connections Program	4/2/2007
TSMC 65-nm Libraries Support Common Power Format-Enabled Design Flow	3/28/2007
Cadence Global Route Environment Technology Offers New Approach to PCB Design	3/26/2007
Ubicom Selects Cadence Encounter Timing System for Timing and Signal Integrity Sign-off	3/26/2007
Cadence Digital IC Design Platform Enables Global Unichip to Complete Taiwan's First 65-nm Chip Design	3/12/2007
Faraday Uses Encounter Conformal Technology for Constraint Signoff of ASIC Designs	3/7/2007
Four Asian Chip Design Companies Adopt Cadence Encounter Tools	2/28/2007
3Leaf Networks Streamlines Logic Design Team Verification With Cadence Incisive Formal Verifier	2/5/2007
Cadence Helps Jennic Tape Out Leading-Edge ZigBee IC, Reducing Chip Area and Power Usage	1/31/2007
Freescale Uses Cadence Analog Mixed Signal Kit to Speed Up Flow Development	1/31/2007
Cadence Delivers Complete Low-Power Solution; Leverages Si2-Approved Common Power Format	1/29/2007
STMicroelectronics Tapes Out 65-nm Mixed-Signal Design Using Cadence Space-Based Router	1/26/2007
Renesas Adopts Cadence Encounter RTL Compiler for ASIC Designs at 90nm and Below	1/23/2007
Si2's Low Power Coalition Receives Common Power Format Parser Source Code	1/17/2007
Ubicom Chooses Cadence Incisive Formal Verifier for Logic Design Team Verification	1/4/2007
Cadence Enhances Encounter RTL Compiler	12/19/2006
Cadence Incisive Formal Verifier Helps UPEK Improve Design Team Productivity	12/19/2006
Wipro Selects Cadence as Primary Vendor for VLSI and System Design Solutions	12/13/2006
New Cadence Virtuoso Custom Design Platform Features TSMC 90-nm RF Process Design Kit	12/12/2006
Cadence and Advantest Address Zero-Defect Testing Requirements for Automotive Electronics	12/5/2006
MegaChips LSI Solutions Adopts Incisive Xtreme to Improve Design Team Verification Process	12/5/2006
Cadence Enterprise System-Level Verification Enables Predictable Software, Hardware and System Quality	12/4/2006
Common Power Format Contributed by Cadence to Si2 Ahead of Schedule as a Result of Significant Customer Input	12/4/2006
Incisive Palladium III Productivity Enables High Performance Enterprise System-Level Verification	12/4/2006
SiRiFIC Wireless Readies Two 3.5G RF Transceivers for Market Using Cadence Logic Design Technology	11/27/2006
Cadence Announces Winners of the Collaborations Award for Excellence in Advancing Design Chain Alliances	11/20/2006
Cadence Aligns with IBM to Accelerate ASIC Design with Cadence Logic-Design Team Technology	11/13/2006
Cadence and SMIC Collaborate to Address Wireless Design Challenges in China	11/10/2006
Cadence and UMC Collaborate to Achieve Wireless Reference Design Silicon Success for Customers	11/6/2006
Global Unichip Tapes Out Five 90-nm Chips with Cadence Encounter Synthesis and Implementation	11/6/2006
Cadence and Si2 Collaboration Paves the Way to a Unified Low-Power Standard	11/2/2006
Six New IP Providers Join Cadence OpenChoice	11/2/2006
The MathWorks Introduces Link for Cadence Incisive	10/31/2006
Freescale Continues Successful Migration to Cadence Encounter Test	10/26/2006
Azul Systems Adds Cadence Encounter Test to Its Design and Manufacturing Test Flow	10/25/2006
Cadence Expands Design Chain Through Encounter Test Collaboration with Source III	10/25/2006
ARM and Cadence Collaborate on Testability Requirements of ARM Partners with Encounter Test	10/24/2006
NEC Improves Product Quality; Lowers Manufacturing Costs wWith Cadence Encounter Test	10/24/2006
Cadence Logic Design Team Solution Addresses Front-End Design "Predictability Crisis"	10/23/2006
Redback Networks Selects Cadence Xtreme III System for Verification Tests	10/17/2006
Si2's Low-Power Coalition to Have Access to Common Power Format	10/5/2006
Cadence Develops Lithography-Aware Design Flow in Collaboration with Brion and Clear Shape	10/2/2006
Cadence Announces Availability of Design-In IP Portfolio for Memory Designs	9/18/2006
Amkor Selects Cadence Technologies for SiP Design Centers Worldwide	9/13/2006
Cadence Lowers Design Team Barriers for Broad Deployment of Hardware Assisted Verification	9/13/2006
Cadence "Reinvents" Virtuoso Platform	9/11/2006
Cadence and SMIC Deliver 90-nm Low-Power Solution for Energy-Efficient SoC	9/7/2006
Fujitsu Delivers ARM9E Processors for ASIC Designs Using Cadence Encounter RTL Compiler	9/7/2006
Cadence Announces Encounter Timing System for Advanced Timing Signoff Analysis	9/5/2006
Fujitsu Adopts Cadence Encounter Timing System for Signoff Timing Analysis	9/5/2006
Power Forward Initiative Broadens Industry Support, Accelerates Standardization of Common Power Format	9/5/2006
Toshiba Adopts Cadence QRC Extraction for 65-nm Design Flows	8/28/2006
X-FAB Selects Cadence Solution for Maximum Yield	8/22/2006
Realtek and Cadence Address Verification with Cadence Encounter Conformal Technologies	8/15/2006
Dongbu Electronics and Cadence Jointly Develop Process Design Kit to Support High-Voltage BCDMOS Chips	8/11/2006
Cadence Introduces Universal Verification Components	8/7/2006
Amalfi Semiconductor Turns to Cadence Kit to Speed Product Development for Cell Phones	7/31/2006
Siemens Expands Its Use of Cadence Incisive Formal Verifier to Improve Time to Market	7/31/2006
Power Forward Initiative Expands and Invites EDA Companies to Join Advisory Group	7/21/2006
Cadence and TSMC Accelerate 65-nm Design with TSMC Reference Flow 7.0	7/19/2006
Cadence Extends Test and Yield Diagnostics Capabilites	7/12/2006
Oki Standardizes on the Cadence Incisive Formal Verifier	7/12/2006
Ansoft's Nexxim Included in Cadence Connections Program	7/5/2006
Cadence Test and Formal Verification Technology Speed Time to Market for Matrox	7/5/2006
Agere Systems Tapes Out Next-Generation, 90-nm Mobile Solution Chip Using Cadence X Architecture	6/28/2006
Denali's Databahn Memory Controller IP Supports Cadence Encounter Synthesis	6/28/2006
ARC and Cadence Announce Optimized Integration of Encounter Digital IC Platform with ARChitect Processor Configurator	6/26/2006
Cadence and ARM Deliver Kit to Speed Verification Closure for ARM Processor-Based Designs	6/26/2006
Cadence Delivers New Space-Based, Full-Chip Router for Advanced Mixed-Signal and Custom Digital Designs	6/26/2006
Freescale Tapeout Marks 1,000th Design for Cadence CeltIC NDC	6/21/2006
Comit Systems Expands Adoption of Cadence Encounter Digital IC Design Technology	6/20/2006
Cadence Debuts Transaction-Based System Verification and Management Solution	6/12/2006
TSMC Production-Ready for 65-nm X Architecture Designs	5/25/2006
UMC Announces Readiness for 65-nm X Architecture Designs	5/25/2006
Dongbu Electronics Collaborates with Cadence to Deliver RTL-GDSII Reference Flow	5/24/2006
Cadence Initiative Aims to Enable Architectural Innovation and Exploration for More Power-Efficient Devices	5/22/2006
TSMC Adds Cadence Technologies for 65-nm Design	5/17/2006
Cadence Releases Reference Methodology for New ARM Cortex-R4 Processor	5/15/2006
Fastrack Design Standardizes on Cadence Fire & Ice QX Extraction	5/1/2006
Cadence and PDF Solutions to Collaborate on IC DFM Products and Roadmap	4/26/2006
Cadence Continues Product-Segmentation Strategy with Allegro Silicon-Package-Board Platform	4/26/2006
Saifun Semiconductors Adopts Cadence Analog Mixed-Signal Methodology Kit	4/26/2006
Cadence Encounter Global Synthesis Supported by STMicroelectronics for Its ASIC Customers	4/25/2006
New Cadence Incisive Enterprise Technology Eases Creation of Verification Scenarios	4/24/2006
Agere Systems Standardizes on Cadence Virtuoso and Incisive Palladium Technologies to Speed Time to Market for 90- and 65-nm Semiconductors	4/19/2006
Cadence and Teranetics Collaborate on Design of 10-Gbit Ethernet Chips Using X Architecture	4/18/2006
Cadence Virtuoso Platform Speeds Time to Market for Zarlink's Ultra Low-Power SOCs	4/18/2006
SMIC and Cadence Deliver New Analog Mixed-Signal Reference Flow to Speed Fabless Chip Design	4/13/2006
Renesas Electronics Gets up to 2X Design Productivity Increase with Cadence Virtuoso NeoCircuit	3/29/2006
Cadence Virtuoso Platform Provides 10x Improvement in Verification Time for VIS	3/27/2006
Hitachi Communication Technologies Speeds Time to Market for ASIC Designs with Cadence Synthesis	3/27/2006
Cadence Incisive Xtreme Server Helps Speed Delivery of Sun's Breakthrough Processor Technology	3/21/2006
IEEE Recognizes Cadence Leadership and Contributions to IEEE 1800 SystemVerilog Standard	3/14/2006
EMA Expands Into IC Market as a Cadence Channel Partner	3/10/2006
New Cadence "Knowledge System" Speeds Adoption and Customization of Incisive Plan-to-Closure Methodology	3/7/2006
Test Insight Addresses Improved Design-for-Test Flow with Cadence	3/7/2006
Cadence and CEVA Collaborate to Deliver Verification Process Automation	3/1/2006
Cadence and Moscow Institute of Electronic Technology Conclude Joint Education Project	2/28/2006
Cadence Collaborates with IBM and Chartered to Deliver 90-nm Low-Power, Yield-Aware Reference Flow	2/27/2006
Cadence Encounter Platform Speeds Volume Production for STMicroelectronics' HDTV Decoder	2/22/2006
Tensilica-Cadence Encounter RTL-to-GDSII Methodology Streamlines SoC Design with Diamond Standard Processor Cores	2/22/2006
Cadence Expands Design for Manufacturing Offering with Solution for Lithography-Aware Design	2/13/2006
Cadence Virtuoso Speeds Design and Verification of Sirific's 3.5G Cellular Transceivers	2/6/2006
Cadence Announces Plans for Global Series of Events to Connect with Users	2/2/2006
austriamicrosystems Releases Further Improved High-Voltage CMOS Process Design Kit for Foundry Customers	2/1/2006
Cadence Unveils Advanced Manufacturing-Aware Chip-Optimization Technology	1/30/2006
VeriSilicon Tapes Out Flip-Chip Design with Cadence Encounter	1/23/2006
Cadence Selected by MIET to Ramp Up Russian Startup Ecosystem	1/17/2006
VIA Tapes Out 90-nm Designs with Cadence Encounter Digital IC Design Platform	1/17/2006
Ponte Solutions Joins Cadence Connections Partnership Program	1/4/2006
Cadence and Sun Extend Collaboration and Announce Broad Support for EDA Applications	1/3/2006
Intersymbol Deploys Cadence Encounter Platform in Mixed-Signal Flow to Cut Design Cycles, Die Area	12/21/2005
Cadence Delivers Major Upgrade for SoC Verification in Incisive Enterprise Family	12/19/2005
Faraday Successfully Completes a Range of 130-nm Tapeouts with Cadence Encounter	12/19/2005
Inphi Tapes Out High-Speed Flip-Chip Design with Cadence Encounter Platform	12/13/2005
Cadence Delivers New RF Design Kit Targeting Customer Design Challenges in Wireless	12/12/2005
Cadence Introduces New Encounter RTL Compiler GXL	12/5/2005
New Cadence Encounter Conformal Low Power GXL Addresses Customer Verification Challenges	12/5/2005
New Cadence SoC Encounter GXL Addresses Customers' Nanometer Design Yield and Variation Challenges	12/5/2005
Cadence Introduces Incisive Enterprise, Linking Multiple Specialists and Languages	11/14/2005
Initial Ballot to Make e Language an IEEE Standard Passes with Flying Colors	11/14/2005
MatrixOne Announces Support of OpenAccess 2.2 for Enhanced Chip Design Collaboration	11/14/2005
Tower Semiconductor Collaborates with Cadence to Deliver Optimized Reference Flow for Specialty Technology Processes	11/14/2005
Hitachi Communication Technologies Chooses Cadence Incisive Enterprise Palladium II	11/9/2005
Kawasaki Micro Improves Timing, Area, Power of ASICs with Cadence Encounter Synthesis	11/8/2005
MediaTek Successfully Adopts Cadence Design Constraint Solution	11/7/2005
Cadence Advances Segmentation Strategy with 3 Tiers of Verification Products and Methodologies	10/24/2005
Cadence Provides Low-Risk SystemVerilog Verification from Plan to Closure	10/24/2005
Cadence Backs User Demand for Accelerating IEEE P1647 e Standardization	10/17/2005
Cadence and UMC Sign Agreement to Streamline Wireless Design in the Fabless Market	10/6/2005
Cadence Aligns Capabilities for Consumer and Mobile Applications to Support ARM's Cortex-A8 Processor	10/4/2005
Toshiba Tapes Out First UniversalArray Chip with Cadence Encounter	10/4/2005
Cadence Announces New Capabilities to Simplify and Accelerate PowerPC Design	9/26/2005
Comit Systems Speeds Time to Market with Cadence Synthesis	9/26/2005
ARM and Cadence Optimize Digital SoC Design Through Expanded Collaboration	9/12/2005
Cadence Delivers on First Milestone in Kits Strategy	9/12/2005
Cadence Formulates New Product Segmentation and Technology to Address Growth in Chip Complexity	9/12/2005
New Cadence Physical Verification System May Change Physical Verification Paradigm	9/12/2005
Berkeley Design Automation Joins the Cadence Connections Program	9/8/2005
Cadence Announces Support for Industry-Standard OpenAccess 2.2 Database	9/8/2005
ITRI Tapes out Low-Power DVFS Test Chip With Cadence Encounter Synthesis and Implementation	9/8/2005
Elan Microelectronics Validates Libraries and Memories Using Cadence Encounter Conformal Custom Technology	9/7/2005
Cadence Enables SensorDynamics to Reduce Design Cycles and Speed Successful Tapeout	8/31/2005
HiSilicon Technologies Collaborates with Cadence and SMIC	8/24/2005
Latest Advances in Cadence IC Packaging Technology Further Tighten Design Cycle	8/22/2005
Cray Accelerates Development of Next-Generation Supercomputer Using Cadence Virtuoso Layout Migrate and Engineering Services	8/15/2005
Fujitsu to Ship Initial Production Volumes of New Structured ASIC Built Using Cadence Encounter	8/1/2005
Global UniChip Improves Quality of Silicon with Cadence Synthesis Technology	7/31/2005
Sunplus Shrinks DVD Chip Size, Design Time and Cost with Cadence Encounter RTL Compiler	7/31/2005
Cadence Helps Sequans Achieve Early Time to Market with Wireless Broadband Chip Tapeout	7/26/2005
OrCAD Technology Enhancements from Cadence Improve Efficiency for Scalable PCB Design	7/26/2005
New Cadence Allegro PCB Design Technology Shortens Design Time and Strengthens Design Chain	7/25/2005
Essence Technology Reduces Synthesizable Area by 30 Percent with Cadence Encounter RTL Compiler	6/14/2005
Nethra Speeds Tapeout of Image Processor with Cadence Encounter RTL Compiler	6/14/2005
Agere Adds Palladium II After Rollout of TrueAdvantage Converged Access Solutions	6/13/2005
ATI, Cadence and TSMC Produce Industry's First Fabless X Architecture Chip	6/13/2005
Cadence Encounter Platform Now Available on 64-Bit Intel Xeon Processor-Based Systems	6/13/2005
Cadence Outlines ''Enterprise VPA'' Strategy to LinkiDesign and Verification Specialists	6/13/2005
Gradient Brings Temperature Awareness to Physical Implementation	6/13/2005
Cadence Supports TSMC Reference Flow 6.0 to Accelerate 65-Nanometer Design	6/9/2005
Cadence Delivers 50% Power Savings in Latest STARC Production Flow	6/8/2005
Virage Logic and Cadence Further Enable Low-Power Design	6/8/2005
Cadence, IBM, Chartered Continue Collaboration to Enable 90-Nanometer Designs	5/25/2005
New Cadence PowerMeter Technology Enables Signoff-Quality Dynamic Power Rail Verification	5/25/2005
Cadence and Faraday Announce Library Collaboration for Nanometer Design	5/10/2005
Ricoh Tapes Out 90nm Chip Early with Cadence Encounter RTL Compiler	5/10/2005
Cadence Unveils Incisive Formal Verifier	5/2/2005
DesignAdvance Joins Cadence Connections Program	4/28/2005
Cadence PCI Express Solution Passes PCI-SIG Compliance Testing	4/25/2005
Concept Engineering Improves Transistor-Level Debugging and Optimization Using Cadence Virtuoso Schematic Editor Environment	4/14/2005
Cadence Contribution to Accellera Boosts Efforts to Standardize IC Design Kits for Designers	3/22/2005
Open-Silicon Licenses Multiple RaSer Serial Link Cells Under the Cadence-Rambus Reseller Program	3/22/2005
Wipro Technologies Adopts Cadence Design Systems for Nanometer Designs	3/16/2005
X-FAB Collaborates with Cadence to Accelerate Analog and Mixed-Signal Designs	3/10/2005
Cadence Delivers First Full-Chip Test Technology	3/7/2005
Collaborative PCB Design Challenges Tackled by New Cadence Partitioning Technology	3/7/2005
Enhanced Signal Integrity Analysis Addresses Low-Power Design Challenges	3/7/2005
Latest OrCAD Technology from Cadence Strengthens Scalable PCB-Level Design	3/7/2005
ZFoundry Collaborates with Cadence on Process Design Kits for Analog and Mixed-Signal ICs	3/7/2005
DongbuAnam Offers Cadence PDK to Speed Design of Analog Functions in Mixed-Signal Chip Designs	3/2/2005
Cadence and Virage Logic Collaborate to Deliver Timing and Signal Integrity Views to Enable Low-Power Design	2/28/2005
GUC Tapes Out Seven Nanometer Designs with Cadence Encounter Technology	2/24/2005
Cadence Launches Organization to Bolster Exchange of Ideas and Information	2/23/2005
Cadence Donates Technology to IEEE to Enhance SystemVerilog Usability	2/14/2005
Cadence, IBM and Rising Collaborate to Enable Leading-Edge SCDMA/GSM RF IC Transceiver	2/3/2005
Cadence First Encounter Global Physical Synthesis Wins IEC DesignVision Award	2/2/2005
Sanyo Achieves Success Tapeout of Digital Consumer Product Using Cadence Encounter RTL Compiler	1/26/2005
Fujitsu Successfully Completes 66 Consecutive Designs with Cadence Encounter	1/25/2005
Cadence Introduces New Mixed-Signal and RF Capabilities to Address Wireless Design Challenges	1/24/2005
CoWare Integrates SPW into Cadence System-to-IC Flow	1/24/2005
Cadence Meets Design Constraint Challenges with Enhanced Encounter Conformal Technology	1/17/2005
Oki Tapes Out with New Cadence Synthesis Low-Power Technology	12/20/2004
Toshiba Supports Cadence Encounter RTL Compiler for ASIC Design Flow	12/13/2004
Azul Implements High-Speed Chip with Cadence Encounter	12/1/2004
Cadence Joins with IBM to Launch Power.org	12/1/2004
Chartered and Cadence Qualify Fire & Ice QX for Leading-Edge Process Technologies	11/15/2004
Sandwork Design Offers Fast Analog, Mixed-Signal Waveform Support for Cadence Virtuoso Platform	10/28/2004
Cadence and ARM Tackle Signal Integrity Issues for Foundry Program Partners with New Views	10/27/2004
Toshiba Implements Its Largest Semiconductor Design to Date with Cadence Digital IC Flow	10/27/2004
New Palladium II Extends Cadence's Position in Acceleration/Emulation	10/25/2004
Cadence Announces Comprehensive Assertion-Based Verification Solution	10/18/2004
Magma and Cadence Establish Timing Model Standard	10/18/2004
PalmChip Qualifies Cadence Encounter Synthesis for AcurX SOC Platform	10/11/2004
New Scalable OrCAD Technology from Cadence Further Tightens PCB Design Process	10/4/2004
Renesas Electronics Standardizes on Cadence MaskCompose	9/29/2004
Cadence Allegro System Interconnect Design Platform Customized for Use with Intel's PCB Design-in Kit	9/8/2004
UMC and Cadence Deliver Digital Reference Flow for Advanced Processes	9/7/2004
Shanghai Research Center for IC Design and Cadence Introduce New CPU/DSP Core-Based Methodology for SOC Chips	8/31/2004
Cadence Accelerates Time to Market for Stretch	8/30/2004
ATI Selects Cadence Incisive Palladium System for Verification of Multimedia SOCs	8/18/2004
Cadence Incisive Palladium System Cuts NVIDIA's Verification Time	8/17/2004
Cadence Virtuoso UltraSim Simulator Speeds Verification of TelASIC's Mixed-Signal Design	8/16/2004
Cadence Announces New OrCAD Technology	8/11/2004
Fujitsu Enters Global Partnership with Cadence to Create Advanced SOC Design Environments	8/3/2004
ATI Implements Radeon X800 Series with Cadence Encounter	7/21/2004
New Release of Cadence Allegro System Interconnect Design Platform Helps Increase PCB Engineer Productivity	7/19/2004
Cadence and Rambus Sign Agreements to Deliver Portfolio of High-Speed Serial Link Solutions	7/15/2004
Cadence Delivers Advanced Verification Environment for Palladium Acceleration/Emulation System	7/15/2004
Atmel Adopts Cadence Virtuoso UltraSim FastSPICE Simulator for Verifying Complex Mixed-Signal Designs	7/13/2004
Enhanced Cadence Virtuoso Platform Delivers Broader Capabilities to Speed Custom IC Design	7/12/2004
Cadence Announces High-Capacity PCB Simulation Tool for Multi-Gigahertz Signal Design	6/23/2004
Cadence Delivers New Allegro Design Workbench	6/16/2004
Cadence and ASML Sign Multi-Year Business Agreement to Develop Advanced DFM Solutions	6/7/2004
Cadence Announces First Encounter Global Physical Synthesis	6/7/2004
Toshiba to Start Production of First SoC With the X Architecture	6/7/2004
TSMC and Cadence Tackle Low Power Challenges at 90 Nanometers and below with New TSMC Reference Flow	6/7/2004
Cadence and CoWare Deliver Electronic System-Level Design-for-Verification Flow	6/1/2004
Cadence Encounter Platform Supports Virage Logic Structured-ASIC Design Libraries	6/1/2004
Synfora Joins Cadence Connections Program to Provide Tightly Integrated Algorithm-to-Tapeout Synthesis	6/1/2004
Cadence to Open Research and Development and Customer Support Center in Russia	5/26/2004
Cadence and EMA to Provide Free ActiveParts Online Database for OrCAD Customers	5/24/2004
Cadence Delivers 90-nanometer Reference Flow to Optimize Nanometer Design for IBM, Chartered Process Platform	5/24/2004
Aspex Semiconductor Uses Cadence Encounter Platform to Implement 130nm Linedancer Processor	5/18/2004
Cadence Brings Timing to the Manufacturing Floor	5/18/2004
Cadence Introduces NanoRoute Super-Threaded Route Acceleration	5/18/2004
UMC and Cadence Deliver Analog Reference Flow for Mixed-Signal Designs	4/19/2004
TSMC Qualifies Cadence Encounter RTL Compiler for Next-Generation Reference Flow	4/13/2004
Toshiba Implements 8-Million-Gate Networking Switch Using Cadence Encounter Digital IC Design Platform	4/12/2004
Cadence to Acquire Neolinear	4/6/2004
Cadence and MIPS Technologies Deliver Encounter Reference Methodology for 32-Bit Core Family	4/5/2004
Cadence Selects Denali Verification IP for PCI Express Designs	3/31/2004
Rising Accomplishes 10 Gbps Optical Transmission IC Tapeout in Record Time with Cadence Virtuoso Platform	3/31/2004
Sigrity Announces Support of New Cadence Allegro System Interconnect Design Platform	3/15/2004
Agere Systems Uses Cadence Encounter RTL Compiler Synthesis for ASIC Customers	3/9/2004
Motorola Implements 90nm Wireless Signal Processor Using Cadence Encounter Digital IC Design Platform	3/9/2004
Procket Networks Standardizes on Cadence Encounter RTL Compiler for Its Synthesis Tool of Choice	3/9/2004
New Cadence Allegro Platform Tackles High-Speed System Interconnect Design	3/8/2004
Agilent Technologies Implements 90nm Digital Signal Processor Using Cadence Encounter Digital IC Platform	3/5/2004
Magma Joins the Cadence Connections Program	3/2/2004
Cadence Enhances Virtuoso Platform	3/1/2004
Cadence Selected to Sponsor New Design Academy in Korea	2/24/2004
Cadence Delivers Encounter RTL Compiler Ultra with Support for VHDL	2/17/2004
Cadence and ARM Upgrade Quality of Silicon Results for ARM Partners with RTL Compiler Synthesis	2/16/2004
Cadence Supports 64-Bit Intel Itanium 2-Based Platforms Running Linux	1/19/2004
eInfochips Selects Cadence Incisive Verification Platform	1/13/2004

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