Atrenta is a provider of broad-based design analysis solutions based on industry standard SpyGlass technology. Atrenta’s design analysis tools deliver early design closure by eliminating downstream design problems and iterative discoveries. This transforms design closure from a set of disjoint events late in implementation stage to a continuous process jumpstarted early in RTL design phase. This leads to improved predictability and efficiency in SoC design phases including RTL design, IP reuse, Verification, logical and physical Implementation. Atrenta has over 100 customers including the world's top 10 semiconductor companies.

SOCcentral Feature Articles
Vendor-Independent RTL Memory BIST Insertion and Verification	10/23/2012
Understanding Formal Verification Concepts-Part 3	1/31/2012
Understanding Formal Verification Concepts-Part 2	1/16/2012
Understanding Formal Verification Concepts	12/9/2011
Handling Clock Synchronization During Power-Driven Synthesis	10/27/2011
Articles Online
Guidelines for Early Power Analysis	2/11/2013
Seismic Shifts Await EDA in a More-than-Moore World	12/20/2012
Power Awareness in RTL Design Analysis	7/23/2012
A Practical Approach to IP Quality Inspection	9/26/2011
Facilitating At-Speed Test at RTL: Part 2	4/20/2011
Facilitating At-Speed Test at RTL: Part 1	4/12/2011
SOC DFT Verification With Static Analysis and Formal Methods	11/17/2010
Will IP Use Increase In Forthcoming SOC Design?	11/4/2010
Design Quality and Its Impact On Design Closure	7/30/2010
Power Analysis of Clock Gating at RTL	6/17/2010
Verification and Generation of Constraints	8/13/2009
Changing SoC Design Methodologies to Automate IP Integration and Reuse	7/27/2009
Preserving the Intent of Timing Constraints	5/17/2008
Critical Clock-Domain-Crossing Bugs	4/2/2008
Understanding Clock Domain Crossing Issues	12/24/2007
Timing Constraints Generation Technology	5/17/2007
New EDA Tools Improve Low Power Design	2/19/2007
Solving the Toughest Problems in CDC Analysis	8/28/2006
A Systematic Approach to Verifying FSMs	10/27/2005
Reducing False Errors in Clock-Domain Crossing Analysis	1/17/2005
Tackling Multiple Clocks in SoCs	3/17/2004
Moving DFT to RTL Overcomes Test Vector Issues	3/3/2003

Tutorials, White Papers, etc.

Assertion-Based Verification: Choosing the Right Solution

Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification

EDA Tools
1Team:Implement	Design Suites
1Team:Verify	Formal Verification
1Team:Analyze Predictive Analysis	Functional Verification

News
Atrenta Ships 5.1 Release of SpyGlass Platform	6/10/2013
Atrenta and Mentor Collaborate on SOC Power Sign-off	5/30/2013
Atrenta India Announces New R&D Facility in Noida	5/13/2013
frobas Chooses SpyGlass CDC for SOC Design Flow	4/22/2013
IPextreme Announces Atrenta as First EDA Company to Join Constellations	1/9/2013
Atrenta Ships 5.0 Release of SpyGlass Platform	12/4/2012
Atrenta and TSMC Announce SpyGlass IP Kit 2.0 Availability	10/30/2012
Atrenta Acquires NextOp Software	6/20/2012
Atrenta Introduces Fast Lint for SpyGlass	6/4/2012
Atrenta Ships 4.7 Release of SpyGlass Platform	5/2/2012
Atrenta Offers IP Kit Spring-Cleaning Promotion	4/16/2012
Atrenta and TSMC IP Quality Initiative Gains Broad Industry Acceptance	3/5/2012
Atrenta Joins Cadence System Realization Alliance	10/24/2011
Atrenta SpyGlass Used in TSMC Soft IP Qualification Flow	5/26/2011
Atrenta, Cadence and SpringSoft Sponsor Free Exhibits Floor Passes and "I LOVE DAC" Campaign	5/26/2011
imec and Atrenta Develop Exploration Flows for 3D ICs	5/25/2011
STARC Adopts Atrenta's Advanced RTL Power and Deep Submicron Test Solutions	5/19/2011
Atrenta's SpyGlass 4.5 Release Adds Numerous New Features	5/16/2011
Atrenta and CEA-Leti Sign a Multi-Year Collaboration Agreement	10/27/2010
Atrenta and TSMC Develop Soft IP Qualification Flow	10/25/2010
Atrenta Announces SpyGlass-Physical for Early Implementation Analysis	6/17/2010
Atrenta's SpyGlass-CDC Solution Reduces Design Risk for Fujitsu Microelectronics Europe	6/2/2010
Arasan Joins Atrenta's SpyLinks Partner Program	2/17/2010
STARC Collaborates with Atrenta on EDA Tool Quality Management System	2/1/2010
NEC Electronics Adopts Atrenta SpyGlass for Early Testability and Low-Power Design	1/25/2010
Atrenta SpyGlass-Constraints SDC Equivalence Verification Capability Adopted By STARC	12/2/2009
Atrenta's SpyGlass-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies	11/17/2009
Atrenta Announces Major Extensions to 1Team-Genesis Platform	7/31/2009
Atrenta and Mentor Graphics Collaborate on Power Optimization for High-Level Synthesis	7/14/2009
Atrenta Collaborates with Sonics and Denali on a 1Team-Genesis Reference Flow to Accelerate SOC Assembly	7/8/2009
Atrenta SpyGlass-MBIST Adopted by STMicroelectronics for RTL Memory BIST and Repair Insertion	6/12/2009
DS2 Adopts Atrenta SpyGlass for Advanced ASIC Design	3/2/2009
Tieto Joins Atrenta's SpyLinks Partner Program	2/25/2009
Atrenta's SpyGlass-CDC Solution Boosts IP Integration Efficiency for Atheros	2/10/2009
Atrenta Announces "SpyGlass Clean" Flow with Leading ESL Synthesis Providers	11/10/2008
Tensilica Joins Atrenta's SpyLinks Partner Program	9/30/2008
Socle Adopts Atrenta’s SpyGlass-DFT Product	9/3/2008
Atrenta Announces 1Team-Genesis Product and Collaboration with STMicroelectronics	6/9/2008
Atrenta Unveils GuideWare Methodologies to Accelerate Adoption of Its Early Design Closure Solutions	6/9/2008
Atrenta Announces SpyLinks Alliance Program	5/28/2008
STARC Adds Atrenta Tools to Reference Flow	4/24/2008
PLX Technology Embraces SpyGlass-CDC for RTL Sign-off	4/16/2008
Atrenta Announces Design-for-Test Solution for Deep Submicron Circuits	3/10/2008
TES Electronic Solutions Standardizes on Atrenta's SpyGlass Design Analysis Platform	4/30/2007
Atrenta Gains Key Patents for Chip Design Analysis Technologies	2/22/2007
Atrenta Donates Low Power Constraint Format to Accellera	11/8/2006
Cray Adopts Atrenta's SpyGlass Platform for Next Generation ASIC Projects	10/31/2006
Atrenta Secures $16M in Series D Funding	10/19/2006
STMicroelectronics Turns to Atrenta for Its Early Design Closure Solution	7/21/2006
Atrenta Introduces Comprehensive C/C++ Analysis for Embedded Software Design	6/13/2005
Atrenta Introduces Predictive Analysis Solution, Providing Earlier, Better Optimization of Chip Designs	5/4/2005
Atrenta Predictive Development Solutions Reduce Risk, Boost Innovation	4/4/2005
Atrenta Releases 1Team Implement to Improves RTL Prototyping, Design and Floorplanning	4/4/2005
TSMC Selects Atrenta as Reference Flow 5.0 Partner for Power Closure and IC Integration Flows	6/7/2004
Atrenta Teams Up With VSI Alliance to Develop an Automated Method to Validate IP Quality	5/10/2004
Atrenta Selects Transfer Nederland as Distributor in BeNeLux Region	2/12/2004
Toshiba Japan Selects Atrenta's SpyGlass to Identify Critical Design Problems at RTL	2/4/2004

Go directly to Atrenta, Inc. for more company and product information.