Sigrity's fast electromagnetic field computation methodologies enable dynamic electromagnetic analysis of an entire chip, package or board. Through simultaneous circuit, package and board co-simulation, these methodologies analyze system-level power and signal performance, and help ensure integrity from die to die through IC packages and across boards.

SOCcentral Feature Articles
… But Will It Work?	9/2/2008
On-Chip Power Integrity, Including Package Effects	3/11/2005

Tutorials, White Papers, etc.

A Design Methodology for the I/O Power Supply of Next Generation Packaging

A Simulation Study of Simultaneous Switching Noise

Achieving 3.2 Gb/s, 400 MTS AGTL+ IO Through Robust Power DeliveryDesign with Minimal Package Size

Bumpless Build-Up Layer Packaging

Distributed Models for Multi-Terminal Capacitors – Using 2D Lossy Transmission-Line Approach

Effective Decoupling Radius of Decoupling Capacitor

Effects of 20-H Rule and Shielding Vias on Electromagnetic Radiation from Printed Circuit Boards

Effects of Power and Ground Via Distribution on the Power and Ground Performance of C4/BGA Packages

Efficient Signal and Power Integrity Analysis Using Parallel Techniques

Extraction of Equivalent Circuit Models of Package Power Supply Distribution Systems from Full Wave EM Field Simulations

Frequency Dependencies of Power Noise

High Speed DDR Performance in 4 vs 6 Layer FCBGA Package Design

Impact of High Impedance Mid-Frequency Noise on Power Delivery

Integrated Modeling Methodology for Core and I/O Power Delivery

Measured and Simulated Signal Propagation Behaviour on High Speed Nets ofLarge, Highly Dense and Complex PCBs

Measurement and Simulation of Simultaneous Switching Noise in the Multi-Reference Plane Package

Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards with Multiprocessor Modules and Verification by Measurements

Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card

Package and Chip Design Optimization for Mid-Frequency Power DistributionDecoupling

Power Delivery System Performance Optimization of a Printed Circuit Boardwith Multiple Microprocessors

Signal Integrity

Simulation Study of Power Delivery Performance on Flip-Chip Substrate Technologies

System-Level I/O Power Modeling

Via and Return Path Discontinuity Impact on High Speed Digital Signal Quality

EDA Tools
CoDesign Studio	Design Suites
PowerDC	Power Analysis
Broadband SPICE	Signal Integrity
PowerSI	Signal Integrity
SPEED2000	Signal Integrity
XcitePI	Signal Integrity

News
Cadence Acquires Sigrity	7/3/2012
Sigrity Introduces XcitePI Chip I/O Interconnect Model Extraction and Assessment Tool	5/14/2012
Sigrity Awarded U.S. Patent for Unique Voltage-Management Optimization	3/5/2012
Sigrity Expands Global Sales and Support Operations	1/30/2012
Synopsys Collaborates with Sigrity to Accelerate Signal-Integrity Analysis	1/25/2012
Sigrity Introduces T2B for Transistor-to-Behavioral-Model Conversion	9/6/2011
Sigrity Partners with TSMC on Reference Flow 12.0	6/2/2011
Sigrity Takes High-Speed Chip-to-Chip Analysis to Next Level with SystemSI	6/1/2011
TSMC Selects Sigrity as a Reference Flow 11.0 Partner	6/29/2010
Sigrity Introduces Pre-Layout System-Level Power Delivery Optimization	5/26/2010
Sigrity Introduces Electrical and Thermal Co-Simulation Tool	2/1/2010
Sigrity Announces XtractIM Version 3.0 for IC Package Modeling	7/23/2009
Teklatech’s FloorDirector Tool Compatible with Sigrity’s XcitePI Power-Integrity Simulation Flow	2/25/2009
Sigrity Unveils Breakthrough Channel Designer Solution	1/21/2009
Sigrity Solution for Multi-Domain I/O Planning Delivers Unified Data Model for Real-time Evaluation	5/21/2007
Sigrity Power Delivery System Platform Delivers Analysis, Verification and Cost-Driven Optimization for High-Speed PCB and IC Package Designs	3/5/2007
Sigrity Now Supports 64-bit Linux Computing Platforms	1/16/2007
Sigrity Adds Parallel/ Distributed Computing Feature to PowerSI Solution	1/8/2007
Sigrity's Unified Package Designer Adopted by STATS ChipPAC for Use in Design Centers Worldwide	11/13/2006
Sigrity Introduces New Suite of Tools to Streamline Package Analysis	10/23/2006
Agere Systems Adopts Sigrity's Unified Package Designer for Single and Multi-die Package Design	8/4/2006
Sigrity's New Physical Design Solution Accelerates Throughput and Reduces Design Errors in High-Density Packages	3/27/2006
NEC Adopts Sigrity's Chip-Package Co-Design Solutions for Dynamic Power Analysis	2/27/2006
Sigrity Enters IC Package Physical Design Market by Acquiring Technology License from Synopsys	2/7/2006
Sigrity Tools Optimize IR Drop Analysis for Packages and Boards	5/31/2005
Sigrity's CoDesign Studio Optimizes Performance of Chip/Package Power Delivery Systems	5/16/2005
Sigrity Enters High-Speed IC Market with XcitePI	3/17/2005
Amkor Partners with Sigrity to Enhance SoC Power Delivery Performance	11/18/2004
Sigrity Enters High-Speed IC Market with Power Integrity Solution	5/17/2004
Sigrity Announces Support of New Cadence Allegro System Interconnect Design Platform	3/15/2004
Sigrity Announces Accurate Co-Simulation Capabilities for High-Speed Design	1/14/2004

Go directly to Sigrity, Inc. for more company and product information.