News |
Altera and TSMC Collaborate on 55-nm EmbFlash Process | 4/15/2013 |
Cadence and TSMC Strengthen Collaboration on Design Infrastructure for 16-nm FinFET Process Technology | 4/8/2013 |
ARM and TSMC Tape-Out First ARM Cortex-A57 Processor on TSMC's 16-nm FinFET Technology | 4/2/2013 |
TSMC Optimizing 16-nm FinFET Design Flows Using Imagination' PowerVR GPUs to Drive Mobile Performance | 3/25/2013 |
Global Unichip Unveils New 28-nm Data Converter IP Family | 3/19/2013 |
Dolphin Integration Announces Availability SpRAM Generator for TSMC 55 LP Process | 3/4/2013 |
Altera and TSMC Continue Long-Term Partnership | 2/26/2013 |
Kilopass NVM IP Proves Manufacturability and Process Control Tolerance on TSMC's 20-nm CMOS-Process Test Chips | 12/4/2012 |
Sonics Participates in TSMC's Soft IP Kit 2.0 Beta Program | 11/20/2012 |
Dolphin Integration's Audio Codec Passes TSMC IP9000 Level-4 40-nm Low-Power Certification | 11/9/2012 |
Atrenta and TSMC Announce SpyGlass IP Kit 2.0 Availability | 10/30/2012 |
eSilicon Offers Specialty Memory Products on TSMC 28-nm and 40-nm Processes | 10/30/2012 |
Dolphin Integration's IP Offerings Support TSMC's Low-Leakage Devices on 180-nm eLL Process | 10/29/2012 |
Berkeley Design Automation Analog FastSpice Platform Incorporated in TSMC 20-nm Custom Design Reference Flow | 10/17/2012 |
Mentor Graphics Provides Design, Verification and Test Solutions for TSMC's 20-nm Design Infrastructure | 10/16/2012 |
SpringSoft's Third-Generation Laker Custom IC Design Platform Included in TSMC's 20-nm Custom Design Reference Flow | 10/16/2012 |
TSMC Selects Cadence Virtuoso and Encounter Platforms for Its 20-nm Design Infrastructure | 10/16/2012 |
Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC CoWoS Reference Flow | 10/15/2012 |
Synopsys and TSMC Collaborate for 20-nm Reference Flow | 10/15/2012 |
TSMC Tapes Out First CoWoS Test Vehicle Integrating with JEDEC Wide I/O Mobile DRAM Interface | 10/15/2012 |
TSMC Validates Cadence 3D-IC Technology for Its CoWoS Reference Flow | 10/15/2012 |
Synopsys and TSMC Deliver 3D-IC Design Support | 10/11/2012 |
TSMC 20-nm and CoWoS Reference Flows Enable Next-Generation Chip Designs | 10/9/2012 |
TSMC Unveils Foundry's First 100-MHz Access Speed Embedded Flash IP | 8/16/2012 |
TSMC and ASML Reach Agreement to Develop Next-Generation Lithography Technologies | 8/6/2012 |
ARM and TSMC Collaborate to Optimize Next-Generation 64-bit ARM Processors for FinFET Process Technology | 7/23/2012 |
Analog Devices and TSMC Collaborate on New Analog Process Technology Platform | 6/20/2012 |
Cadence Collaborates with TSMC on 3D-IC Design Infrastructure | 6/4/2012 |
Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20-nm Phase I Certification | 6/4/2012 |
Cadence Physical Verification System Qualified for TSMC 28-nm and 20-nm Processes | 6/4/2012 |
ATopTech Place-and-Route Receives TSMC 20-nm Phase I Certification | 5/31/2012 |
Synopsys Design Implementation Tools Receive TSMC 20-nm Phase I Certification | 5/31/2012 |
Mentor Graphics Calibre SmartFill Addresses TSMC 20-nm Fill Requirements | 5/30/2012 |
Renesas Electronics and TSMC Collaborate to Construct Ecosystem for Microcontrollers | 5/28/2012 |
Mentor DFM Analysis Service Delivers Calibre Litho Checks for TSMC 40-nm and 28-nm Processes | 5/24/2012 |
TSMC's 28-nm ARM Cortex-A9 Test Chip Reaches Beyond 3GHz | 5/3/2012 |
ARM Expands Processor Optimization Pack Solutions for TSMC 40-nm and 28-nm Process Variants | 4/16/2012 |
Dialog Semiconductor and TSMC Create Process Platform for BCD Power Management | 3/29/2012 |
Altera and TSMC Jointly Develop Heterogeneous 3D IC Test Vehicle Using CoWoS Process | 3/22/2012 |
Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nm Processes | 2/16/2012 |
Arteris, TSMC Collaborate on Interposer Test Chip Projects | 12/12/2011 |
TSMC 28-nm Technology in Volume Production | 10/24/2011 |
ARM and TSMC Tape Out First 20-nm ARM Cortex-A15 Multicore Processor | 10/18/2011 |
Cadence Library Characterization Scripts Now Available in New TSMC Reference Kit | 10/17/2011 |
Mentor Graphics and TSMC Address Advanced Node Fill Requirements Using Calibre SmartFill | 9/15/2011 |
Sidense's NVM IP Completes TSMC IP9000 Assessment at 90-nm Low-Power Process Node | 9/13/2011 |
eSilicon and TSMC Support Long-Lifecycle Products | 8/18/2011 |
Duolog Technologies Joins TSMC Reference Flow 12.0 | 8/9/2011 |
Sidense Completes TSMC IP9000 Assessment for SiPROM NVM IP | 8/2/2011 |
eMemory Offers eNVM IP in TSMC 80-nm High-Voltage Technology | 7/13/2011 |
TSMC Qualifies Magma's QCP Extractor for 28-nm Designs | 7/13/2011 |
Snowbush IP Group Launches New Multi-Standard PHY IP Platform on TSMC 28-nm Process | 7/12/2011 |
Arteris Joins TSMC Reference Flow 12.0 with Flexnoc Network-on-Chip (NoC) Interconnect IP | 6/8/2011 |
Cadence Collaborates with TSMC on New 28-nm Flows | 6/7/2011 |
Cadence Extends IP Offering; Collaborates with TSMC via Open Innovation Platform | 6/7/2011 |
Magma Announces Availability of Titan Analog Design Kit for TSMC 180/65-nm Nodes | 6/7/2011 |
Carbon Design Systems Performance, Power Analysis Tools Added to TSMC Reference Flow 12.0 | 6/6/2011 |
Ciranova Helix Provides 28-nm Support for TSMC AMS Reference Flow 2.0 | 6/6/2011 |
Mentor Graphics Addresses 28nm and 3D-IC Requirements in TSMC Reference Flow 12 | 6/6/2011 |
Mentor Graphics Delivers Essential New Capabilities in TSMC AMS Reference Flow 2.0 | 6/6/2011 |
Mentor Graphics Provides Calibre Verification and Tessent Test Solutions for 3D-IC in TSMC Reference Flow 12 | 6/6/2011 |
MunEDA WiCkeD Supports TSMC AMS Reference Flow 2.0 for 28nm | 6/6/2011 |
Sonics Announces Support for TSMC's Reference Flow 12 | 6/6/2011 |
SpringSoft's Laker Custom Layout System Selected for TSMC 28-nm Reference Flows | 6/6/2011 |
Synopsys and TSMC Collaborate to Deliver Custom Design Solution for 28nm TSMC AMS Reference Flow 2.0 | 6/6/2011 |
Apache's Power, Noise, and Thermal Solutions Included in TSMC Reference Flow 12.0 and AMS Reference Flow 2.0 | 6/2/2011 |
Berkeley Design Automation Analog FastSpice Deployed in TSMC AMS Reference Flow 2.0 | 6/2/2011 |
Lorentz Solution's PeakView Supports TSMC RF Reference Design Kit 3.0 | 6/2/2011 |
Sigrity Partners with TSMC on Reference Flow 12.0 | 6/2/2011 |
ATopTech's Aprisa Included in TSMC Reference Flow 12.0 for 28-nm Designs | 6/1/2011 |
Magma's Talus IC Implementation System Supports TSMC 28-nm Reference Flow 12.0 | 6/1/2011 |
Magma's Titan and FineSim Validated for TSMC's Analog/ Mixed-Signal Reference Flow 2.0 for 28-nm Processes | 6/1/2011 |
Solido for Variation Analysis and Design in TSMC Analog/Mixed-Signal Reference Flow 2.0 | 6/1/2011 |
Synopsys Delivers 28-nm Design Solutions and Advanced System-Level Capabilities for TSMC Reference Flow 12.0 | 5/31/2011 |
Atrenta SpyGlass Used in TSMC Soft IP Qualification Flow | 5/26/2011 |
TSMC Completes 28-nm Design Infrastructure | 5/26/2011 |
TSMC Joins SEMATECH to Accelerate Semiconductor Technology Development | 5/11/2011 |
Cadence and TSMC Collaborate to Deliver DFM Services for TSMC Advanced Processes | 5/9/2011 |
Cosmic Circuits Announces Proven 65-nm MIPI PHY IP for TSMC Technology | 5/9/2011 |
Mentor Graphics Partners with TSMC to Validate Advanced Functional-Verification Technology | 5/5/2011 |
Sidense Completes TSMC IP9000 Assessment for Non-Volatile Memory (NVM) Product Families | 4/5/2011 |
Synopsys Announces Availability of DesignWare PHY and Embedded Memory IP for TSMC 28-nm Technologies | 3/30/2011 |
Mentor Graphics Teams with TSMC to Enrich Reference Flow 11 Low-Power Verification Solutions | 3/28/2011 |
ATopTech Place-and-Route Engine Included in TSMC's EDA 28-nm Routing Qualification Report | 3/22/2011 |
Spreadtrum and TSMC Achieve 3G TD-SCDMA Baseband Processor Milestone | 1/28/2011 |
NetLogic Microsystems Achieves First Silicon Tape-Out in TSMC's Advanced 28-nm Process | 1/17/2011 |
Synopsys' IC Validator Completes Qualification for TSMC's 40-nm and 65-nm iDRC/ iLVS Physical Verification | 11/17/2010 |
Atrenta and TSMC Develop Soft IP Qualification Flow | 10/25/2010 |
Arteris Joins TSMC Soft IP Alliance | 10/13/2010 |
Chips&Media Joins TSMC's Soft-IP Alliance Program | 10/13/2010 |
MIPS Technologies Joins TSMC IP Alliance | 10/13/2010 |
MIPS Technologies Joins TSMC IP Alliance | 10/11/2010 |
Sonics Joins TSMC's Soft IP Alliance Program | 10/11/2010 |
Vivante Joins TSMC IP Alliance Program | 10/11/2010 |
TSMC Expands IP Alliance to Include Soft IP | 10/6/2010 |
Synopsys Galaxy Implementation Platform Used by TSMC for 28-nm Process | 8/9/2010 |
ARM and TSMC Sign Long-Term Strategic Agreement Enabling Processor and Physical IP Optimization on TSMC's Advanced Nodes | 7/21/2010 |
TSMC Announces Automotive-Qualified 0.25-Micron One-Time-Programmable IP | 6/30/2010 |
TSMC Selects Berkeley Design Automation Analog FastSpice Transient Noise for TSMC AMS Reference Flow 1.0 | 6/30/2010 |
Carbon Design Systems Announces Performance, Power Analysis in TSMC Reference Flow 11.0 | 6/21/2010 |
Mentor Graphics Provides Comprehensive Verification Support in TSMC AMS Reference Flow 1.0 | 6/17/2010 |
SpringSoft's Laker Custom Layout Automation System Validated for TSMC 28-nm AMS Reference Flow | 6/17/2010 |
TSMC New Standard Cell Slim Library Reduces Logic Area 15% | 6/17/2010 |
TSMC Selects EdXact Jivaro for 28-nm AMS Reference Flow | 6/17/2010 |
Cadence Delivers Extensive Support for TSMC AMS Reference Flow 1.0 for 28-nm Process | 6/14/2010 |
Magma's Talus IC Implementation System Supports TSMC 28-nm Process Technology Through Reference Flow 11.0 | 6/11/2010 |
Synopsys Delivers Comprehensive Custom Design Solution for TSMC Analog/ Mixed-Signal Reference Flow 1.0 | 6/11/2010 |
TSMC Selects Solido for Variation-Aware Custom IC Design In Analog/ Mixed-Signal Reference Flow 1.0 | 6/11/2010 |
TSMC Extends Open Innovation Platform | 6/7/2010 |
TSMC Announces 0.18-µm Automotive Grade Embedded Flash IP | 5/31/2010 |
TSMC, Mentor and Synopsys Donate iDRC to Si2 | 5/28/2010 |
SpringSoft's Laker Layout Supports TSMC 40-nm Technology with Interoperable PDK | 5/26/2010 |
Magma’s Titan Mixed-Signal Platform Supports TSMC’s 65- and 40-nm Interoperable PDKs | 5/18/2010 |
NetLogic Microsystems and TSMC Collaborate on 28-nm Process Technology | 5/3/2010 |
Azuro’s Low-Power CTS Tool Included in TSMC’s Second Integrated Sign-off Flow Release | 4/14/2010 |
TSMC Expands Cadence Tool Support In Integrated Sign-Off Flow By Adding Synthesis, Place and Route, and RC Extraction | 4/14/2010 |
TSMC Delivers Interoperable EDA Formats for Advanced Process Technologies | 4/6/2010 |
TSMC Expands Physical Verification Support In Integrated Sign-off Flow with Magma Quartz DRC and Quartz LVS | 4/6/2010 |
Mentor Graphics Calibre LFD Certifications at TSMC Now Include 28-nm Process Node with TSMC UDFM Engine | 3/23/2010 |
ATopTech's Aprisa Physical Design Solution Qualified by TSMC for 40-nm Designs | 1/19/2010 |
Qualcomm and TSMC Collaborating on 28-nm Process Technology | 1/11/2010 |
TSMC Helps LSI Reduce Leakage 25% on Next-Generation Product | 1/8/2010 |
TSMC Announces Process Technologies for Integrated LED Drivers | 12/18/2009 |
TSMC Selects Calibre Physical Verification Platform for Integrated Sign-off Flow | 10/22/2009 |
Agilent Technologies' Momentum Electromagnetic Simulator Qualified for High-Frequency Designs in TSMC Advanced RF Processes | 10/14/2009 |
Lorentz Solution's Electromagnetic Design and Verification Solution Certified to Support TSMC iRCX Format for Advanced Process Nodes | 10/2/2009 |
Cadence Physical Verification System Supports TSMC's Interoperable iDRC and iLVS Formats for 40-nm Design | 10/1/2009 |
Magma Broadens Support for TSMC 180-nm Processes | 10/1/2009 |
Mentor Graphics Provides Comprehensive Low-Power Solution in TSMC Reference Flow 10.0 | 9/21/2009 |
Fujitsu Microelectronics and TSMC to Collaborate on 28-nm Process Technology | 8/27/2009 |
TSMC Achieves 28nm SRAM Yield Breakthrough | 8/25/2009 |
TSMC Adds High-K Metal Gate Low-Power Process to 28-nm Road Map | 8/25/2009 |
Magma's Talus Included in TSMC Reference Flow 10.0 Targeting 28-nm Process Technology | 7/29/2009 |
TSMC and Global Unichip Collaborate On Silicon Proven SiP Solution in TSMC Reference Flow 10.0 | 7/29/2009 |
Cadence Delivers 28-Nanometer Design Capabilities to TSMC Reference Flow 10.0 | 7/28/2009 |
TSMC and Cadence Expand Collaboration to Deliver Advanced, Feature-Rich Process Design Kits | 7/27/2009 |
Ciranova PyCell Technology Included in TSMC iPDK for Analog/ Mixed-Signal IC Design | 7/23/2009 |
Magma's Titan Mixed-Signal Platform Supports TSMC's Interoperable Process Design Kit (iPDK) | 7/23/2009 |
Synopsys Galaxy Implementation Platform Supports TSMC 28-nm Process Technology with Reference Flow 10.0 | 7/23/2009 |
TSMC Extends Design Methodology to 28nm with Reference Flow 10.0 | 7/23/2009 |
Synopsys and TSMC Jointly Develop Interoperable Process Design Kit (iPDK) and Interoperable Ecosystem | 7/22/2009 |
TSMC Launches Unified Physical Verification Format for Advanced Process Technologies | 7/22/2009 |
Virage Logic Offers Broadest Portfolio of Embedded Non-Volatile Memory (NVM) Solutions at TSMC | 7/21/2009 |
NetLogic Microsystems and TSMC Collaborate on 40-nm Technology for Next-Generation Processors and 10/40/100 Gigabit Physical Layer Solutions | 7/16/2009 |
NXP and TSMC Deliver Industry's First 45nm Single-Chip Digital TV Platform | 7/9/2009 |
TSMC Unveils 65-nm Multi-Time Programmable Non-Volatile Memory Technology | 7/2/2009 |
TSMC Enhances 0.13-µm Family | 6/29/2009 |
Synopsys and TSMC Deliver Accurate Lithography Verification for 28-nm Designs | 6/23/2009 |
SpringSoft and TSMC Begin Joint Development of Multi-Node Process Design Kit Portfolio | 6/22/2009 |
TSMC Reports Foundry's First 28nm Low-Power Platform Technology with Fully Functional 64-Mbit SRAM | 6/19/2009 |
Cadence QRC Full Chip Extractor Qualified for TSMC's Interoperable (iRCX) Format for 65- and 40-nm Design | 6/10/2009 |
TSMC Launches Unified Interconnect Modeling Format for Advanced Process Technologies | 5/28/2009 |
Fujitsu Microelectronics and TSMC to Collaborate on Leading-edge Process Technology | 5/4/2009 |
Cadence and TSMC Introduce Mixed-Signal/ RF Reference Design Kit in 65-nm Process Technology | 4/23/2009 |
TSMC Launches Integrated Sign-Off Flow to Shorten Design Cycle, Enhance Tape-Out Quality | 4/23/2009 |
TSMC and GUC 65LP ARM 1176JZF Hardened Cores Open Doors for 65-nm Designers | 4/22/2009 |
TSMC Qualifies New 0.18-Micron Embedded Flash Family | 4/1/2009 |
Ciranova and TSMC Announce Strategic Partnership on Advanced PDK Technology | 3/24/2009 |
Intel to Port Atom CPU Cores to TSMC’s Technology Platform | 3/4/2009 |
Mentor Graphics Olympus-SoC Place-and-Route System Qualifies for TSMC 40-nm Processes | 12/11/2008 |
TSMC Ramps 40-nm Volume Production | 11/18/2008 |
TSMC Adds New High Voltage Features to 0.13-µm Processes Aimed at High-Resolution Display Drivers | 11/6/2008 |
MAPPER and TSMC to Explore Multiple E-beam Lithography for IC Manufacturing at 22nm and Beyond | 10/16/2008 |
TSMC Adopts Mentor Graphics Calibre Equation-Based DRC Feature for Advanced Physical Verification | 10/8/2008 |
Virage Logic and TSMC Expand Agreement to Provide Process-Optimized IP | 10/1/2008 |
TSMC's 28nm to Be a Full-Node Process | 9/29/2008 |
Mentor Graphics Eldo Adopted by TSMC for Cell Library Characterization of 40-nm | 8/13/2008 |
Mentor Graphics Provides Advanced Design For Manufacturing Capabilities in TSMC Reference Flow 9.0 | 6/13/2008 |
TSMC Reference Flow 9.0 Covers Apache's Advanced Leakage and System Jitter Analysis | 6/12/2008 |
Cadence Delivers Advanced DFM Solutions, Statistical Analysis and Low-Power Design Technology for TSMC Reference Flow 9.0 | 6/11/2008 |
Magma Talus and Quartz Software Qualified for 40-nm in TSMC Reference Flow 9.0 | 6/5/2008 |
New TSMC Reference Flow 9.0 Supports 40-nm Process Technology | 6/4/2008 |
Mentor Graphics Qualifies Calibre Model-Based Planarity Flow for TSMC's 65- and 40-nm Processes | 5/30/2008 |
TSMC Unveils New 40/ 65-nm Spice Tool Qualification Program | 4/22/2008 |
Virage Logic Delivers Complete Memory Compiler and Logic Library IP Portfolio for TSMC 40-nm Process | 4/7/2008 |
TSMC First to Deliver 40nm Process Technology | 3/24/2008 |
Magma Volcano Supports TSMC 45-nm and 65-nm IC Implementation | 2/27/2008 |
Sun Selects TSMC to Fab Future Generation of UltraSPARC CMT Processors | 2/21/2008 |
Integrand Joins TSMC's 65-nm RF Tool Qualification Program | 2/18/2008 |
TSMC Announces Multi-layer Mask Service | 12/27/2007 |
TSMC Reports Foundry's First 32-Nanometer Technology with Functional SRAM | 12/12/2007 |
TSMC Unveils New 65-nm Mixed-Signal and RF Tool Qualification Program | 12/12/2007 |
NetLogic Microsystems and TSMC Collaborate on 55-nm Technology for Advanced Low-Power Knowledge-based Processors | 11/27/2007 |
Mentor Graphics and TSMC Collaborate to Release 65-nm RF Design Kits | 11/13/2007 |
Magma's Quartz DRC Runsets Qualified for TSMC's 45-nm Process Technology | 11/6/2007 |
TSMC Starts Production of 0.13-Micron Embedded Flash Process | 8/21/2007 |
Microsoft Taps TSMC 90-nm Embedded DRAM Process for Xbox 360 | 8/15/2007 |
Analog Devices and TSMC Bring 65-nm Technology to SoftFone Baseband Processors | 7/10/2007 |
Kilopass Announces Collaboration with TSMC in Embedded NVM Technology | 7/9/2007 |
TSMC and Cadence Collaborate on 65-nm Design Flow for Wireless Designs | 6/26/2007 |
Cadence QRC Extraction Tool Qualifies on TSMC's 45-nm Process Technology | 6/5/2007 |
Mentor Graphics Collaborates with TSMC to Provide Advanced DFM Capabilities in Reference Flow 8.0 | 6/5/2007 |
Magma Software in TSMC Reference Flow 8.0 Qualified for 45-nm Process Technology | 6/4/2007 |
Synopsys Supports TSMC Reference Flow 8.0 to Address 45-nm Design Challenges | 6/4/2007 |
TSMC Announces Active Accuracy Assurance Initiative | 6/4/2007 |
TSMC Unveils Reference Flow 8.0 to Address 45-nm Design Challenges | 6/4/2007 |
AMD Chooses TSMC 65-nm Process for GPU Product Line | 5/23/2007 |
Spansion and TSMC Sign Joint Development Agreement to Expand MirrorBit Applicability at 40nm and Below | 5/15/2007 |
K-micro Runs Digital TV Devices on TSMC 90nm Embedded RAM | 5/9/2007 |
Cadence Accelerates 45-nm Design with TSMC Reference Flow 8.0 | 5/4/2007 |
Virage Logic Named as TSMC's 45-nm Process Early Development IP Partner | 4/10/2007 |
TSMC 45-nm Design Ecosystem Now in Place | 4/9/2007 |
Virage Logic Becomes First Semiconductor IP Vendor with Silicon Proven Memory on TSMC's 65-nm GP Process | 4/5/2007 |
TSMC 65-nm Libraries Support Common Power Format-Enabled Design Flow | 3/28/2007 |
TSMC Announces 55-nm Half-Node Process Technology | 3/27/2007 |
TSMC and Synopsys Announce CCS Model Support for TSMC'S 65-nm Process | 3/6/2007 |
NetLogic Microsystems Leverages TSMC 80-nm GC Process for Highest Performance Knowledge-Based Processor | 2/26/2007 |
MoSys and TSMC Extend 1T-SRAM Embedded Memory Licensing Agreement | 2/5/2007 |
ARM Announces First Production-Ready DDR1 And DDR2 Memory Interface IP on TSMC 90-nm Process | 12/19/2006 |
Mentor Graphics Calibre xRC and Calibre xL Tools Validated for TSMC 65-nm Process Technology | 12/14/2006 |
New Cadence Virtuoso Custom Design Platform Features TSMC 90-nm RF Process Design Kit | 12/12/2006 |
Mentor Graphics and TSMC Provide TSMC-Qualified Process Design Kit for 0.13-Micron Mixed-Mode and RF Design | 11/30/2006 |
GDA Technologies Accepted into TSMC's Design Center Alliance Program | 11/3/2006 |
ARM Announces Release of Multiple Standard Cell Libraries on TSMC 90-nm and 65-nm Processes | 10/25/2006 |
SST and TSMC Collaborate on Development and Licensing of Next-Generation 90nm SuperFlash Technology | 8/28/2006 |
TSMC Qualifies Mentor Graphics Calibre nmDRC on 65-nm Process | 7/28/2006 |
Magma IC Implementation Software Integrated into TSMC Reference Flow 7.0 | 7/21/2006 |
TSMC and ARM Collaboration Achieves Significant Power Reduction on First 65-nm Low-Power Test Chip | 7/21/2006 |
TSMC Reference Flow 7.0 Incorporates Synopsys' IC Compiler | 7/21/2006 |
Apache Supports TSMC Reference Flow 7.0 in Critical Areas of Power and Noise Management | 7/19/2006 |
Cadence and TSMC Accelerate 65-nm Design with TSMC Reference Flow 7.0 | 7/19/2006 |
TSMC Introduces Reference Flow 7.0 | 7/19/2006 |
Synopsys Introduces Validated USB 2.0 nanoPHY IP for TSMC's Nexsys 90-LP Process | 6/28/2006 |
TSMC Qualifies Anchor Semiconductor's Product for Lithography Process Check in Layout-to-Silicon Patterning | 6/28/2006 |
Mentor DFT Tools Fully Support TSMC's Reference Flow 7.0 | 6/21/2006 |
TSMC Production-Ready for 65-nm X Architecture Designs | 5/25/2006 |
Magma Enhances DFM Product Offering with Blast Yield TX and New LPC Capabilities in Quartz DRC | 5/17/2006 |
Mentor Graphics Calibre Platform Provides Integrated DFM Flow for TSMC 65-nm Technologies | 5/17/2006 |
Synopsys Partners with TSMC to Offer Comprehensive DFM Solution for Yield Enhancement | 5/17/2006 |
TSMC 65-nm Process Moves to Volume Production | 5/17/2006 |
TSMC Adds Cadence Technologies for 65-nm Design | 5/17/2006 |
TSMC Names Synopsys to Distribute Its Production-Ready 65-nm Nexsys Libraries | 5/17/2006 |
TSMC Unveils 65-nm Data-Driven DFM Design Ecosystem | 5/15/2006 |
Magma's Quartz DRC Qualified on TSMC 90-nm and 65-nm Processes | 4/24/2006 |
ARM and TSMC Sign Long-Term Physical IP Agreement for 65- and 45-nm Technologies | 4/19/2006 |
TSMC 65-nm Wireless Devices Being Sampled by Qualcomm | 4/10/2006 |
TSMC Says Immersion Lithography Nearly Production Ready | 2/22/2006 |
TSMC in Production with 80-nm Process | 1/17/2006 |
SST and TSMC Extend Reach of SuperFlash Embedded Technology Through Expanded Licensing Agreement | 12/12/2005 |
Synopsys Offers First Certified TSMC 90-nm USB 2.0 OTG PHY IP | 12/9/2005 |
TSMC Adopts Synopsys TetraMAX for Yield Diagnostics | 10/24/2005 |
TSMC Completes First 65nm Prototype Runs | 10/5/2005 |
Open-Silicon Joins TSMC's Design Center Alliance | 8/24/2005 |
Spansion and TSMC Team to Manufacture Innovative Flash Memory Technology | 8/11/2005 |
TSMC and Kodak Sign License Agreement for CMOS Image Sensors | 7/8/2005 |
Impinj and TSMC Qualify AEON Memory | 6/20/2005 |
ATI, Cadence and TSMC Produce Industry's First Fabless X Architecture Chip | 6/13/2005 |
Cadence Supports TSMC Reference Flow 6.0 to Accelerate 65-Nanometer Design | 6/9/2005 |
Key Synopsys Low Power and DFM Technologies Support TSMC Reference Flow 6.0 | 6/9/2005 |
TSMC Introduces Comprehensive DFM Toolkits | 6/9/2005 |
TSMC and RMI Collaborate on 90nm Process for New Throughput-Optimized Thread Processor Solutions | 6/7/2005 |
Virage Logic Joins with TSMC to Lead 65nm Ramp | 5/31/2005 |
TSMC Validates 90nm Process Technology with Mentor Graphics Calibre xRC Test Chip Program | 1/12/2005 |
TSMC Announces Nexsys 90nm Volume Production | 12/29/2004 |
Synopsys Galaxy Design Platform Enables First-Pass Silicon Success of Winbond's Latest MPEG-4 Multimedia Chips | 12/13/2004 |
TSMC 0.18-Micron High-Voltage Technology Goes to Volume Production | 11/23/2004 |
ViASIC Announces New 0.13 TSMC Library | 11/8/2004 |
Synopsys Introduces 90nm USB 2.0 On-The-Go PHY and Extends Its Hi-Speed USB PHY to 90nm Node | 8/30/2004 |
TSMC and Apache Address Dynamic Power Closure for Nanometer Design | 6/7/2004 |
TSMC and Cadence Tackle Low Power Challenges at 90 Nanometers and below with New TSMC Reference Flow | 6/7/2004 |
TSMC and Synopsys Address Design Challenges for 90 Nanometer and Below with TSMC Reference Flow 5.0 | 6/7/2004 |
TSMC Reference Flow 5.0 is First to Enable Power Closure | 6/7/2004 |
TSMC Selects Atrenta as Reference Flow 5.0 Partner for Power Closure and IC Integration Flows | 6/7/2004 |
TSMC Joins the X Initiative | 5/17/2004 |
Synopsys and TSMC to Optimize RTL-to-Wafer Design Process
| 4/13/2004 |
TSMC Qualifies Cadence Encounter RTL Compiler for Next-Generation Reference Flow | 4/13/2004 |
TSMC Validates Magma's Capacitance Extraction Accuracy for 0.13-Micron Designs | 4/12/2004 |
TSMC to Supply Products and Services for Future Microsoft Game Consoles | 4/6/2004 |
TSMC Response Identifies More SMIC Espionage | 3/23/2004 |
eSilicon Joins TSMC Design Center Alliance | 3/8/2004 |
TSMC Certifies Synopsys' Star-RCXT for 90-nm Designs | 3/2/2004 |
Synopsys to Distribute TSMC'S Libraries Through DesignWare Library | 2/9/2004 |
TSMC's Low-k Technology Goes Mainstream with Volume Production | 2/3/2004 |
