Page loading . . .

  
 Category: Vendors, Organizations & Universities: Vendors: Friday, May 24, 2013
Sagantec, Inc.  
Address: 2075 De La Cruz Blvd., Suite 105
              Santa Clara, CA 95050
Phone: 408-727-6290
Email: info@sagantec.com
Website: www.sagantec.com


Sagantec is a provider of process-migration solutions for custom IC design. Sagantec's EDA solutions enable IC designers to leverage their investment in existing physical design IP and accomplish dramatic time and effort savings in the implementation of custom, analog, mixed-signal and memory circuits in advanced process technologies.

These solutions have been used commercially by tier-1 semiconductor companies, and have been proven to reduce layout time and effort by factors of 3X to 20X and enable dramatically faster introduction of IC products in new technology nodes.



EDA Tools

Companion

Placement & Routing

Hurricane

Placement & Routing

SiClone

Placement & Routing

SiFix

Placement & Routing

XTREME

Placement & Routing

News

NanGate and Sagantec Collaborate to Automate Standard-Cell Library Creation at 14nm to 22nm

2/13/2013

Vanguard International Semiconductor Adopts Sagantec Migration Solution

6/4/2012

Sagantec Announces New Migration and DRC Correction Tool for 28nm and 20nm

5/14/2012

Sagantec Acquires NP-Komplete Technologies

5/3/2012

Sagantec Speeds Porting of High-Performance Interface IP at MoSys

7/20/2009

Sagantec and TSMC Collaborate on Sagantec DFM-Fix

10/25/2007

Sagantec Announces a New DFM Solution Integrated with Mentor Graphics' Calibre LFD

6/4/2007

Sagantec Provides the "Missing Link" to a Complete DFM Solution

6/26/2006

Sagantec Releases Tool Set Supporting 65nm and 45nm Process Design Rules

6/6/2005

Legend, Sagantec Enable Equator to Migrate and Optimize Custom Embedded Memory from 0.2 micron to 0.13 micron

3/29/2004


Go directly to Sagantec, Inc. for more company and product information.
Keywords: Sagantec, EDA, DFY & Process Models, Library Development, Signal Integrity Analysis,
206/649 1/26/2003 1972 456
Rate this vendor's website (anonymous postings will be deleted)




Designer's Mall
0.53125



 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
190.206  0.609375