Page loading . . .

  
 Category: Vendors, Organizations & Universities: Vendors: Friday, April 25, 2014
Blue Pearl Software, Inc.  
Address: 4677 Old Ironsides Drive, Suite 403
              Santa Clara, CA 95054 USA
Phone: 408-961-0121
Email: info@bluepearlsoftware.com
Website: www.bluepearlsoftware.com


Blue Pearl Software's innovative timing exception generation and validation solution enables ASIC and FPGA designers meet increasingly challenging chip performance goals. Blue Pearl's breakthrough technologies in functional analysis, false and multi-cycle path extraction and verification are optimized to work at blazingly high speeds, allowing designers to generate correct timing constraints early, before synthesis, for today's complex multi-million gate designs. Using Blue Pearl's highly integrated solution, companies can improve quality of results, reduce risks and shorten chip development times with faster timing closure.

SOCcentral Feature Articles

RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology

1/2/2013

New Tools Take the Pain out of FPGA Synthesis

6/29/2012

EDA Tools

Analyze Plus

CDC Verification

Create Timing Constraints

Constraints Management

Analyze RTL

Design Rule Checking

Articles Online

RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology

10/26/2012

News

Blue Pearl Announces User Grey Cell Methodology with the Release of Version 7.1

9/30/2013

Blue Pearl Software Now Available for Purchase Online

9/13/2013

Blue Pearl Software Suite Customized for Xilinx Users

6/10/2013

Blue Pearl Software Suite Now Available for Purchase Through the Embedded Software Store

6/10/2013

Blue Pearl Software Adds STARC Support to Further FPGA RTL Sign-Off

3/18/2013

Blue Pearl Software Advances FPGA RTL Sign-Off, Releases v6.2 with Enhanced Grey Cell Methodology

2/21/2013

Blue Pearl Adds Sales and Support Staff in North American

12/18/2012

Blue Pearl Software Opens Japan Office

12/17/2012

Blue Pearl Demos FPGA Design Tools for RTL Sign-Off at EDSFair

10/31/2012

Blue Pearl Joins ARM Connected Community

10/24/2012

Blue Pearl Advances FPGA Design Automation, Announces Software Release with Enhanced Path Analysis

10/22/2012

Northwest Logic Uses Blue Pearl Software's Analyze to Maximize IP Core Quality

6/4/2012

Blue Pearl Joins Xilinx Alliance Program

5/29/2012

Blue Pearl Announces Support for Synopsys Synplify Pro Design Flow

3/13/2012

Verific Design Automation Selected to Support Blue Pearl Software Suite

2/17/2012

Sibridge Technologies Ensures Maximum IP Reliability with Blue Pearl's Next-Generation Software

6/22/2011

New Blue Pearl Software Suite Transforms IC Design Analysis, CDC Checking, SDC Creation and Validation

1/28/2011

Blue Pearl Software Introduces FPAT for Highest Level of Constraint Confidence

6/11/2010

Blue Pearl Software Announces Cobalt Timing Constraint Management

7/20/2009

Blue Pearl Software Announces Business Partnership Program with Design Service Companies and Consultants

4/16/2009

Blue Pearl Software Launches JumpStart Program for Startups

4/7/2009

Blue Pearl Software Introduces Short-Term EDA Tool Use Plan

1/22/2009

Blue Pearl Softwares Version 4.0 of Cobalt Timing Constraint Generation Speeds Timing Closure

11/19/2008

Blue Pearl Software Announces Azure Timing Constraint Validation

3/31/2008

Blue Pearl Software Introduces Cobalt Timing Constraint Generation Software for Reducing Design Iterations and Risks in IC and IP Development

7/19/2006

Blue Pearl Software Introduces RTL Closure Tool

1/24/2005

Blue Pearl Software to Automate the Process of RTL Closure for IC and Electronic System Design

5/24/2004


Go directly to Blue Pearl Software, Inc. for more company and product information.

Keywords: Blue Pearl Software, EDA, Design Entry and/or Analysis (RTL),
206/6711 5/24/2004 2059 661
Rate this vendor's website (anonymous postings will be deleted)


Designer's Mall
Cinco De Mayo countdown banner
0.6098633



 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Progressive Static Verification Leads to Earlier and Faster Timing Sign-off


Graham Bell
VP of Marketing,
Real Intent

Executive
Viewpoint

Threading the Way
through
SOC Verification


Thomas L. Anderson
VP of Marketing,
Breker Verification Systems

Odd Parity

What? You Haven't Made Any Resolutions?


Mike Donlin
The Write Solution

Odd Parity Archive

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
190.206  0.6721191