Page loading . . .

  
 Category: Vendors, Organizations & Universities: Vendors: Wednesday, June 19, 2013
Apache Design Solutions, Inc.  
Address: 2645 Zanker Road
              San Jose, CA 95134 USA
Phone: 408-457-2000
Email: apache_sales@apache-da.com
Website: www.apache-da.com


Apache Design Solutions is an EDA software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design, such as power, signal, package/ system I/O, substrate, and temperature, Apache’s silicon signoff platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache’s vendor neutral platform enables designers to adopt any industry’s standard physical design flow and is certified by TSMC’s Reference Flow.

SOCcentral Feature Articles

Chip Power Model for Co-Design

7/12/2010

Articles Online

Design for Reliability: The Golden Age of Simulation-Driven Product Design

5/7/2012

A Modeling Approach for Power-Integrity Simulation in 3D-IC Designs

4/27/2012

Design-for-Power Methodology

4/20/2012

Early and Accurate Power Analysis: Myth or Reality?

4/11/2012

An RTL-to-GDSII Approach for Low Power Design: A Design for Power Methodology

1/12/2011

Power Delivery Network Design Requires Chip-package-system Co-Design Approach

3/15/2010

Accurate Thermal Analysis of Chip/Package Systems

3/15/2007

Power Integrity Requires Global I/O SSO Analysis

6/16/2004

Reshaping the SoC Power Design Flow

2/6/2004

NSPICE Bridges Simulation Gap

2/20/2003

Webcasts

Chip-Package Co-Design: Applying Chip Power Model in System Power Integrity Analysis

5/8/2008

Power Analysis Using RedHawk from Early Design to Signoff

5/9/2007

How to Manage Clock Jitter Noise for Accurate Timing Sign-off

2/13/2007

EDA Tools

RedHawk

Power Analysis

SkyHawk

Power Analysis

PsiWinder

Timing Analysis

News

ANSYS and Subsidiary Apache Design Receive TSMC 20-nm Phase I Certification

6/4/2012

Apache Design Releases 4th-Generation Redhawk for Sub-20-nm Power Sign-Off

5/1/2012

Apache Design's Totem Software Adopted by Fujitsu Semiconductor for Power Noise And Reliability Analysis

12/12/2011

Apache Launches RTL Power Model

11/8/2011

ANSYS Announces Successful Closing of Apache Acquisition

8/2/2011

ANSYS to Acquire Apache Design Solutions

6/30/2011

Apache's Power, Noise, and Thermal Solutions Included in TSMC Reference Flow 12.0 and AMS Reference Flow 2.0

6/2/2011

Apache's Power, Noise and Reliability Solutions Selected by Exar for SOC Products

9/14/2010

Apache Chosen By Major CPU/GPU/APU Semiconductor Design Company as Global Supplier for Power Noise and Reliability Sign-Off Tools

6/17/2010

ASE Selects Apache Design Solutions' Products for Chip/ Package/ System Convergence

5/28/2010

Apache Design Solution's Power and Noise Products Adopted by MoSys for IP Validation and Sign-Off

5/20/2010

Apache Introduces PathFinder Full-Chip ESD Physical-Integrity Solution

5/10/2010

Apache Design Solutions' Power and Noise Platforms Adopted by Aptina

4/14/2010

Realtek Semiconductor Adopts Apache Design Solutions' Products for Power and Reliability Signoff

3/16/2010

PLX Technology Adopts Apache Design's Power-Analysis and Optimization Solutions

2/9/2010

Apache's Power and Noise Solutions Adopted by Sigma Designs for Digital Media SOCs

1/25/2010

Apache Design Solutions Acquires Sequence Design

9/10/2009

Apache's Power and Noise Integrity Solutions Certified to Support TSMC's Unified Interconnect Modeling Format

6/11/2009

Apache's RedHawk Power Integrity Solution Adopted by AMCC for SOC and Mixed-Signal Designs

4/29/2009

Apache Design Solutions Introduces Totem Power and Noise Integrity Platform for Analog and Mixed-Signal Designs

4/23/2009

NEC Adopts Apache's Dynamic Power Sign-off Solution for SOC Designs

4/1/2009

Apache and NXP Collaborate to Address 45-nm Power Integrity Challenges for Advanced Digital Processor Design

3/12/2009

Apache Deepens Collaboration with STMicroelectronics

2/20/2009

Apache Design Solutions Introduces Next-Generation RedHawk-NX

1/8/2009

TSMC Reference Flow 9.0 Covers Apache's Advanced Leakage and System Jitter Analysis

6/12/2008

Hynix Adopts Apache's Dynamic Power Integrity Solution for DRAM Designs

6/6/2008

Apache Announces Sentinel-PI, a Global Chip-Package-System Co-Design and Co-Analysis Solution for Power Integrity

5/21/2008

Apache Announces Next Generation PakSi-E, Version 8.1

4/28/2008

Sanyo Semiconductor Adopts Apache's Power Sign-off Solution

4/10/2008

Apache's Power Sign-off Solution Available for 65-nm Common Platform Reference Flows from Chartered, IBM and Samsung

11/6/2007

Toshiba Expands Use of Apache RedHawk as Power Sign-off Solution

9/13/2007

MediaTek and Apache Partner to Address 65/45-nm Design Challenges

9/10/2007

Global Unichip Adds Apache's RedHawk to Its 65-nm Signoff Flow

8/7/2007

TSMC Reference Flow 8.0 Includes Apache's Tools

6/28/2007

Apache Introduces Sentinel Combined Chip-Package Power and I/O Integrity Solution

5/29/2007

Apache Announces RedHawk-ALP Advanced Low Power Solution for 65/45-nm Designs

4/16/2007

Apache Addresses Critical Area of Power and Thermal Management in UMC's 90-nm Reference Design

3/6/2007

LG Adopts Apache's PsiWinder for Full-Chip Clock Jitter and Critical Path Timing Sign-off

2/5/2007

Apache Selected by STMicroelectronics to Address Upcoming 45-nm Design Challenges

1/8/2007

Apache Design Solutions Expands India Operations

10/10/2006

Apache and NEC Electronics Collaborate to Address the System-in-Package (SiP) Power Integrity Challenge

10/3/2006

Apache Announces Sahara-PTE Integrated Power-Thermal-Electrical Solution for SOC Designs

7/21/2006

Apache Supports TSMC Reference Flow 7.0 in Critical Areas of Power and Noise Management

7/19/2006

LG Electronics Adopts Apache's Dynamic Power Closure Solution for SOC Designs

4/12/2006

Apache Addresses Dynamic Power Integrity in STARC's Latest Production Flow

1/23/2006

Kawasaki Microelectronics Adopts Apache's SoC Power Closure Design Flow

10/12/2005

ATI Technologies Signs Multi-Year Agreement with Apache Design Solutions

6/10/2005

Apache Supports TSMC Reference Flow 6.0 with Dynamic Power Integrity for Advanced Low Power Designs

6/9/2005

Apache Introduces PsiWinder, a Combined Power and Signal Integrity Timing Sign-off Tool

6/6/2005

Apache Power Closure Sign-Off Flow Enables First-Pass Silicon Success for Airgo Networks

4/4/2005

Apache's Full-Chip Dynamic Physical Power Integrity Solution Adopted by STMicroelectronics

3/8/2005

Apache Announces RedHawk-EV Physical Power Integrity Solution for Power Closure Sign-off

2/21/2005

Toshiba Adopts Apache's RedHawk-SDL for SOC Power Closure

9/9/2004

Apache's Physical Power Integrity Flow Adopted by ATI Technologies

8/23/2004

Apache's SkyHawk Removes Guesswork from Power Grid Design in Nanometer Chips

6/7/2004

TSMC and Apache Address Dynamic Power Closure for Nanometer Design

6/7/2004

Apache Enhances RedHawk-SDL for Low-Power Designs and Addresses Timing Impact Issues in Nanometer Designs

5/24/2004

Apache Design Solutions Wins EDN Magazine's 2003 Innovation of the Year Award

3/30/2004

Apache's Full-Chip Dynamic Power Integrity Solution Adopted by VIA Technologies

3/3/2004

Apache and Xilinx Unveil Signal Integrity Analysis Tool for Virtex-II Pro Based Multi-Gigabit Serial I/O Designs

2/11/2004

Apache Introduces NSPICE for Power Integrity and Ultrawide Broadband Simulation

1/26/2004


Go directly to Apache Design Solutions, Inc. for more company and product information.

Keywords: Apache Design Solutions, EDA, EMI Analysis, Parasitic Extraction, Spice & Spice-like Simulation (IC), Power Analysis & Optimization, Signal Integrity Analysis, Thermal Analysis,
206/689 1/26/2003 3392 719
Rate this vendor's website (anonymous postings will be deleted)


Designer's Mall
4th Of July countdown banner
0.625



 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
190.206  0.65625