HES-DVM™, a hardware emulation solution, facilitates easy design setup and flexibility with its fully scriptable environment, ASIC to FPGA clock conversion, automatic design partitioning, advanced HDL compiler, incremental compilation and interface with commercial simulators.

SOCcentral Feature Articles
SCE-MI Explained: Macro-based and Function-based	8/24/2012
Clarifying Language/Methodology Confusion in FPGA Design	6/1/2011
Articles Online
Best Design Practices for High-Capacity FPGA Devices	3/4/2013
DO-254: Increasing Verification Coverage by Test	1/9/2013
FPGA Testing for DO-254 Compliance	5/22/2012
Where There's a Will… There’s a Way to Better VHDL Verification	5/21/2012

Tutorials, White Papers, etc.

Clarifying Language, Methodology Confusion

Concurrent FPGA-PCB Design within an Integrated Design Environment

Corporate Standardization of FPGA Design Flow

Debugging SCE-MI Co-Emulation in Riviera-PRO Simulation Environment

Deploying Properties Assertions and Coverage

Embedded Systems Verification

Enhancing Verilog Designs with Embedded PSL

Enhancing Verilog Designs with SVA

Enhancing VHDL Designs with Embedded PSL

HDL Simulation and Mathematical Modeling Integration

HES Simulation Acceleration

HES-7 ASIC Prototyping

Interoperable IP Delivery

Meeting Growing Verification Demands

System Level Design: SystemC Using Transaction Level Modeling

Tool Assessment and Qualification with the Aldec DO-254 Compliance Tool Set

Using FPGA Prototyping Board as an SoC Verification and Integration Platform

Using FPGA-Based Simulation Acceleration In a Typical ASIC Design Flow

Verification of Ethernet Designs with SCE-MI based Aldec Emulator

Virtual Modeling with Aldec and Imperas

Webcasts
Making a Simple, Structured and Efficient VHDL Testbench	4/18/2013
ARM Cortex SOC Prototyping Platform for Industrial Applications	3/14/2013
DO-254 Verification Strategies with Aldec and X-Tek	2/21/2013
Best Design Practices for High-Capacity FPGA Devices	1/24/2013
Aldec-Altera DO-254 Webinar: How to Increase Verification Coverage by Test	9/27/2012
Assertions: A Practical Introduction for HDL Designers	9/1/2012
Efficient Verification of Complex FPGA Designs	9/1/2012
HW/SW Co-Verification: Why Wait for Silicon?	9/1/2012
New Trends in HDL Code Linting	9/1/2012
Transaction Level Co-Emulation with Virtual Platforms	9/1/2012
OS-VVM High-Level VHDL Verification	7/19/2012
Simulation on the Cloud: Unlimited Possibilities	6/28/2012
Better Coverage in VHDL	5/3/2012
Bridging Analog and Digital Verification	3/8/2012
100% Signal Visibility During Emulation Dynamic Debug with HVD Technology	2/16/2012
Closed Loop Verification of Large Designs	12/25/2011
Efficient Verification Approach for DO-254 designs	12/25/2011
Introducing Transactions in Design Verification	12/25/2011
New Mirror-Box Technology for Hardware-Assisted Simulation	12/25/2011
OVM and UVM: Building a SystemVerilog Testbench in Riviera-PRO	12/25/2011
Secure IP Delivery: Practical Introduction for HDL Users	12/25/2011
TLM Concepts for Hardware Designers	12/25/2011
Transaction-Level Visual Debugging	12/25/2011
Decrypting Encryption in HDL Design and Verification	12/1/2011
SystemVerilog: Who? What? When? Where?	8/25/2011

EDA Tools
ALINT Design Rule Checking	DRC/ERC/LVS
Active-HDL	Mixed Verilog/VHDL
Riviera	Mixed Verilog/VHDL
HES-DVM	Prototyping/Emulation

News
Aldec Delivering ALINT 2012.12 Service Release 1	6/10/2013
Aldec Launches Spec-TRACER Requirements Lifecycle Management for Safety-critical FPGA and ASIC Designs	5/20/2013
Aldec to Offer Technical Sessions and Demonstrations at DAC	5/15/2013
Last Days to Participale in Aldec Survey: Driving Innovation for DSP Apps	4/25/2013
Aldec Presents VHDL Testbench Webinar	4/15/2013
Aldec Releases Plot Window to Increase Productivity of Traditional Waveform-Based HDL Debugging	3/11/2013
Aldec Adds Assertions Training to Fast Track Online Program	2/25/2013
Aldec Launches Free Online UVM Training	2/4/2013
Hitachi Cable Deploys ALINT on Next-Generation FPGA Design	1/15/2013
Aldec Emulation and Verification Tools Adopted by Taiwan National Chiao Tung University for ESL Design Master's Program	1/2/2013
Aldec Optimizes FPGA Routing Resources for Power and Performance	1/2/2013
Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform	12/10/2012
Aldec Unwraps SOC/ASIC Verification Platform at Verification Futures Conference	12/6/2012
Creonic Joins Aldec UNITE Partner Program	11/15/2012
Aldec Announces Webinar on ASIC/SoC Prototyping with Aldec's New HES-7 Board	11/12/2012
Aldec Boosts VHDL Simulation Performance	11/5/2012
Aldec Gives SOC Software Engineers Early Access to Hardware	11/5/2012
Aldec to Hold "Don't Be Afraid of UVM" Live Webcast	10/18/2012
Aldec Enhances Award-Winning Active-HDL with Flexible File Management for Complex FPGA Projects	9/24/2012
Aldec Enters ASIC Prototyping Market with HES-7	9/17/2012
Verific Design Automation's SystemVerilog, VHDL Parsers Linked with Aldec's Hardware Emulation Solution	8/15/2012
TVS Validates UVM-Based VIP with Aldec's Riviera-PRO	7/17/2012
Aldec Offers OS-VVM High-Level VHDL Verification Webinar	7/16/2012
Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation Environments	7/10/2012
Aldec Invited to Present "FPGA Level In-Target Testing for DO-254 Compliance" at Avionics Conference in South Korea	7/3/2012
Open-Source-VHDL Verification Methodology (OS-VVM) User Group to Unveil Advanced Test Methodologies for VHDL Designers at DAC	6/4/2012
Aldec at DAC 2012 with 10 Face-to-Face Sessions	5/24/2012
Tanner EDA and Aldec Deliver High-Performance A/MS Solution for Mixed-Signal IC Design and Verification	5/18/2012
Aldec Takes FPGA and ASIC Debugging to the Next Level	3/13/2012
Aldec Adds Documentation for Safety-Critical Designs in ALINT 2012.01	1/23/2012
Aldec and SynthWorks Deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM	1/12/2012
Aldec Delivers Complete Support for UVM 1.1, Enabling VMM and OVM Interoperability	11/16/2011
Aldec Delivers HVD Technology, Providing 100% Visibility During Hardware Emulation	11/16/2011
Aldec Releases Active-HDL 9.1 Supporting Simulation of the Newest FPGA Devices	11/4/2011
Aldec Offers Free Assertions Seminar	7/25/2011
Aldec's Emulation and Verification Tools Adopted by UC San Diego for the New Master's Program in Wireless Embedded Systems	7/25/2011
Aldec Announces 2012 Global Calendar Photo Contest	7/23/2011
Aldec Adds UVM Transaction-Level Visual Debugging	7/11/2011
Aldec, Cadence, Proximus Utilize OVP Fast Processor Models in System Design Solutions	6/6/2011
Aldec and Avnet Asia Pacific Ink Distribution Agreement	6/1/2011
PLDA and Aldec Announce PCI Express DMA IP Supporting Advanced Verification Tools for FPGA Development	4/28/2011
CAST IP and Aldec Simulators Unite for Smoother FPGA and ASIC Design Flow	3/7/2011
Aldec Sponsors Advanced Innovation Laboratory at TsingHua University and Research Center	11/17/2010
Aldec-Israel Established	11/8/2010
Aldec, HighRely and Leading FPGA Vendors Establish DO-254 Ecosystem	9/14/2010
Aldec Announces Phase-Based Linting Methodology	8/9/2010
Northwest Logic Verifies Compatibility of Its IP Cores with Aldec RTL Simulators	8/2/2010
Aldec Supports OVM and UVM in Riviera-PRO	6/21/2010
Latest Release of Aldec's Riviera-PRO Supports OVM/UVM	6/8/2010
Altium Adds Aldec FPGA Simulation Technology to Altium Designer	5/25/2010
Aldec Adds RMM Library and FPGA Primitive Support to ALINT	4/19/2010
Aldec Releases RTL Simulator with Enhanced Assertions and Xilinx SecureIP Support	12/24/2009
Aldec Adds DO-254/ ED-80 Library to HDL Design Rule Checker	12/10/2009
Aldec Announces Low-Cost Linux RTL and Gate-level Simulator	11/17/2009
EMA Partners with Aldec to Provide Cadence OrCAD Users a Complete FPGA Design Solution	10/16/2009
ASICSoft and Aldec Forge Partnership in Northern California	8/13/2009
Aldec Delivers $1,995 Mixed-Language Simulator to FPGA Market	7/13/2009
Aldec Releases ALINT 2008.10 Supporting Mixed VHDL and Verilog Design Rule Checking	12/9/2008
Aldec Delivers New Dual-FPGA Prototyping Solution for Actel RTAX4000S Space-Flight FPGA Designs	12/2/2008
Aldec Releases Unified 64-bit Multi-Threaded HDL Design Environment	11/18/2008
Aldec Announces OVM World Partnership and Future Support for OVM 2.0	11/10/2008
Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1	9/30/2008
Aldec Selected by Thales to Deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System	9/22/2008
Aldec Announces HES 2008.07 with SCI-ME 2.0 Co-Emulation Debugging and Dynamic Debugging for ASIC Design Emulation	7/28/2008
Aldec Delivers Clock Domain Crossing Solution	6/23/2008
Aldec Enhances Entire EDA Suite with Key Verification Methodologies	6/10/2008
Aldec Releases Riviera-PRO 2008.06 HDL Simulator	6/4/2008
Aldec Joins Altera DO-254 Global Partner Network	4/28/2008
Aldec Delivers ASIC Design Emulation with SCI-ME 2.0 Support	4/24/2008
Lattice and Aldec Announce New Alliance for FPGA Design and Verification	4/22/2008
Aldec Launches Verilog Design Rule Checker	3/3/2008
Aldec Releases Riviera-PRO 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI)	2/25/2008
Aldec Releases Active-HDL 7.3 and Introduces Multi-Threaded HDL Compilation	12/20/2007
Zuken and Aldec Launch CADSTAR FPGA	10/31/2007
Aldec Releases STARC Based Linting Tool	6/11/2007
Zuken and Aldec Partner to Offer Complete FPGA Design and Verification Flow	5/23/2007
Aldec Delivers Prototyping Solution for Actel RTAX-S Space FPGA Designs	5/14/2007
Aldec Supports The MathWorks Simulink Fixed Point Types	4/9/2007
Aldec Announces Support for Altera's Low-Cost Cyclone III FPGAs	3/19/2007
Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design	3/12/2007
Aldec Releases 64-Bit Mixed HDL Simulator	3/5/2007
Aldec to Deliver Riviera-Pro to Korea's POSDATA	3/5/2007
Gaisler Research and Aldec Partner to Increase IP Core Availability and Portability	2/21/2007
Lattice and Aldec Sign Mixed-language Simulator Agreement	1/8/2007
Aldec Announces Support for Altera's Stratix III Devices	11/8/2006
Actel and Aldec Partner to Offer High-Reliability Design Solutions for Aerospace and Avionics Markets	11/6/2006
Aldec Extends Code Coverage Analysis Offering	7/21/2006
Aldec Simulators Validated for Use with Lattice Devices	5/15/2006
Altera's Quartus II 6.0 Offers Integrated HDL Support for Aldec's Simulator	5/9/2006
Aldec’s Verilog Simulator Now Supports Sun Microsystems Open-Source UltraSPARC T1 Processor Core	3/30/2006
Aldec Releases Active-HDL 7.1 with New Simulation Technology and SystemVerilog Support	10/31/2005
Aldec Delivers Next Generation of Simulation Technology	10/3/2005
Aldec and Renesas Sign Unlimited Site License Agreement for HDL Simulator	8/15/2005
Aldec Responds to an EDA Paradigm Shift with an Under-$200 High Performance HDL Simulator	8/1/2005
Aldec Releases Riviera 2005.04 with New System-Level Simulation Performance and Debugging	4/18/2005
Aldec Releases Riviera-IPT with Support for ARM926	3/7/2005
Quest Innovations Joins Aldec IP Partner Program	2/11/2005
Aldec Releases Active-HDL Actel Edition	12/13/2004
Aldec and Magma Deliver Seamless Front-to-Back FPGA Design Flow	11/15/2004
Aldec Releases Active-HDL 6.3 with Integrated SystemC Cosimulation	10/19/2004
Aldec Announces System-Level Methodology Training Seminars	9/6/2004
Aldec Brings Mixed VHDL/Verilog/SystemC Verification to Mainstream Designers	8/30/2004
Aldec Announces webXlive for Interactive, Web-Based Demonstrations and One-on-One Support	8/24/2004
Aldec Releases Riviera-IPT Desktop as Affordable Acceleration Solution for RTL Verification	7/14/2004
Aldec Joins Accellera Standards Group	7/6/2004
Aldec Releases Riviera-IPT with Co-Verification support for ARM	6/7/2004
Aldec Joins PSL/Sugar Consortium	5/27/2004
Aldec Accelerates Verification of Altera’s Nios Microprocessor-Based Designs	5/3/2004
QuickLogic Partners with Aldec to Provide Advanced Simulation Capability	4/19/2004
Aldec Selected as HDL Design Entry and Verification Solution for China National IC Base	3/24/2004
Aldec's HDL Simulator Supports Altera's Stratix II Device Family	3/15/2004

Go directly to Aldec, Inc. for more company and product information.