Balsa is an asynchronous circuit synthesis system built around the Handshake Circuits methology and can generate gate- ... read more

JHDL is a method of describing (programmatically, in Java) the components and connections in a digital logic circuit. ... read more

ChipVault is a fast and nimble VHDL and Verilog Chip Design Organization tool which improves design efficiency. ChipV ... read more

Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench. C ... read more

csrGen is a tool to automatically build verilog RTL for the CSRs in processor interfaces of many ASIC/FPGA designs. cs ... read more

The Actel Designer offers an easy to use and flexible solution for all Actel's FPGA devices. It gives designers the fl ... read more

The Actel Designer offers an easy to use and flexible solution for all Actel's FPGA devices. It gives designers the fl ... read more

EDIF (Electronic Design Interchange Format) has become the the world's most widely used electronic design interchange format. ... read more

The POLIS system is centered around a single Finite State Machine-like representation. A Co-design Finite State Machin ... read more

Gates On the Fly (GOF) is a netlist processing tool with graphical and script mode. GOF has four function units: GofVi ... read more