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 Category: Magazine & Journal Articles Online: Current Month: Sunday, May 19, 2013
Enabling High-Performance SOCs Through Multi-Die Reuse  
Publication: Design & Reuse
Contributor: STMicroelectronics
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April 20, 2012 -- This article gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for different performance levels and price points to be achieved. The technique relies on a new high-bandwidth low-pin-count communication channel between two or more dice.

The channel allows the on-chip interconnect to be extended to bridge between chips while allowing other signals to be integrated in a low power manner. This arrangement provides the basis of a family of platforms which supports the integration of multiple chips within a package (or on a board) and permits each die to have been designed independently.

 

By Andrew Jones and Stuart Ryan. (The authors are with STMicroelectronics R&D, Ltd.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

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STMicroelectronics
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Keywords: ASICs, ASIC design, 3D ICs, 3D chips, stacked ICs, packages, packaging, EDA, EDA tools, electronic design automation, Design & Reuse, STMicroelectronics
602/38340 4/20/2012 1237 82


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