Page loading . . .

  
 Category: Magazine & Journal Articles Online: Current Month: Saturday, May 18, 2013
Low Power Is Everywhere  
Publication: Electronic Engineering Times (EE Times)
Contributor: Synopsys, Inc.
 Printer friendly
 E-Mail Item URL

April 18, 2012 -- Meeting power budgets for most system-on-chip (SOC) designs today is no longer a requirement for mobile applications only. Almost every market segment today has some concern with designing in low power features, although the driving factor for why does differ among them. The primary impetus for low-power design was initially driven by the mobile market due to the need for extending battery life; however, different segments do have different reasons for making power a primary design requirement.

Power is now a primary requirement for all designs but it's not just about performance or area anymore and there are several factors that designers need to take into consideration to meet the stringent low power requirements. There are several key components that comprise a low power design and offer methods for controlling power:

  • Technology process selection provides a power vs. performance vs. area trade-off.
  • Architectural and implementation techniques offers power vs. complexity trade-offs.
  • Optimization engines delivers on rapid time-to-market and quality-of-results.

By Mary Ann White. (White is the Product Marketing Director for Galaxy Implementation Platform products at Synopsys, Inc.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Electronic Engineering Times (EE Times) website.

Read more about
Synopsys, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, Synopsys, Electronic Engineering Times (EE Times)
602/38341 4/18/2012 558 71


Designer's Mall
0.171875



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.214  0.2353516