May 26, 2012 -- In many modern applications such as video processing, minimizing FPGA reconfiguration time is critical in order to avoid losing too many images. Partial reconfiguration is a technique that allows users to reconfigure a small part of the FPGA without impacting logical elements around it. For the human eye to see an image without flicker, the reconfiguration time must be less than 40ms. That's very little time to reconfigure an entire device, save for the smallest FPGAs; and in certain specific applications, this reconfiguration time must be even less. Hence the appeal of partial reconfiguration; because a partial bitstream is smaller than a full one, it takes less time to reconfigure. At Sagem DS, we have devised a technique that allows FPGA designers to accomplish partial reconfiguration very fast.
By S. Lamonnier, M. Thoris and M. Ambielle. (The authors are with Sagem DS [Safran Group].)
This brief introduction has been excerpted from the original copyrighted article.
