|
IC Floorplanning and Power Integrity August 2, 2010 -- A previous article, "Continuum (Analog) Analysis of Power Integrity," discussed in some detail power integrity (PI), its significance to low-power/ energy design, and the analog technique for simulating PI. This article continues to discuss the significance of PI to floor planning for SOCs and 3D SiPs. ... read more Selecting an AES Solution August 2, 2010 -- The Advanced Encryption Standard (AES), based on the Rijndael algorithm combines an extremely high level of security with computational efficiency. The algorithm consists of Exclusive-OR functions combined with matrix operations and is a mathematically "clean" design which avoids the risk of "back doors" to unauthorized users. The elegance and efficiency of the system makes it suitable for either hardware or software systems. ... read more Defining a Universal Verification Methodology July 23, 2010 -- There's really no disagreement about the increasing complexity of designing system-on-chip (SOC) devices. It's clear that design is a relatively bounded problem compared to verification. Just as design reuse through semiconductor IP (aka design IP) helped bring the designers up the productivity curve, in the last decade, verification IP (VIP) has done the same for the verification engineers. ... read more Click here for all SOCcentral Feature Articles
| 
