eeDesign is the EDA News section of Electronic Engineering Times (EE Times) Online and is a comprehensive source of information for electronics design tools and methodologies. Its scope includes EDA tools, silicon intellectual property (IP), chip design methodologies, and chip and system architectures. It includes the ISD magazine and Silicon Engineering archives.

Articles Online
RTL-ers Should Move to ESL	10/19/2007
Flexible Constraint-Management Drives Next-Generation Mixed-Signal Design	9/11/2006
SystemVerilog Reference Verification Methodology: VMM Adoption	9/4/2006
Solving the Toughest Problems in CDC Analysis	8/28/2006
Virtual Prototyping Speeds Mixed-Signal IC Design	8/21/2006
Verification IP Takes a Broader Role	8/7/2006
Reducing Cycle Times for Design Rule Checking	7/31/2006
Using Statistical Activity for Power Estimation	7/24/2006
Pulse-Latch Approach Reduces Dynamic Power	7/17/2006
Formal Verification: Where to Use it and Why	7/10/2006
Cell Model Creation for Statistical Timing Analysis	7/3/2006
Constraint-Driven Physical Design Speeds IC Convergence	6/26/2006
Sequential Equivalence Checking for RTL Models	6/19/2006
SystemVerilog Reference Verification Methodology: ESL	6/12/2006
Facilitating System-in-Package (SiP) Design	6/5/2006
A Bridging Model for ESL Synthesis	5/29/2006
How Assertions Can Be Used for Design	5/22/2006
Sequential Equivalence Checking Supports ESL Flow	5/15/2006
OCP "Tags" Support High-Performance SoCs	5/8/2006
SystemVerilog Reference Verification Methodology: RTL	5/1/2006
Temperature-Aware Design for Mixed-Signal ICs	4/24/2006
A Hierarchy of Needs for SoC IP Reuse	4/17/2006
Adapting Signal Integrity to Nanometer IC Design	4/10/2006
FPGA Partial Reconfiguration Mitigates Variability	4/3/2006
SystemVerilog Reference Verification Methodology: Introduction	3/27/2006
A Technical Overview of the CE-ATA Storage Interface	3/20/2006
Facing the Challenges in Analog Design	3/13/2006
System Synchronization Styles and Trends	3/6/2006
The "What" and "Why" of Transaction Level Modeling	2/27/2006
How Much Test Compression is Enough?	2/20/2006
Compiling FPGA Netlists for Formal Verification	2/6/2006
I/O Planning Ensures IC Packaging Success	1/30/2006
Chip Assembly Challenges and Solutions	1/23/2006
How to Choose Custom IC Design Tools	1/16/2006
Critical Area Optimizations Improve IC Yields	1/9/2006
High-Speed PCB Design: Symmetry and Spinoffs	1/2/2006
An Introduction to Symbolic Simulation	12/19/2005
Using SystemVerilog for Functional Verification	12/5/2005
Introduction to XML for Engineering Applications	11/28/2005
Yield Challenges Require New DFM Approach	11/21/2005
Cluster-Based Approach Eases Clock Tree Synthesis	11/14/2005
Tackling Test Challenges for Low-Power Design	11/7/2005
Verifying Large Models in RTL Simulation	10/31/2005
Managing Variations in IC Physical Design	10/24/2005
Test Takes New Role in Yield Improvement	10/17/2005
Static and Dynamic Modeling for High-Density Memories	10/10/2005
Verification Moves to a Higher Level	10/3/2005
The History and Future of Scan Design	9/19/2005
Multiprocessing Speeds IC Physical Verification	9/12/2005
OpenAccess: First Impressions at AMD	9/5/2005
Designing ICs with the "X" Architecture	8/29/2005
Easing Verification Challenges for IP Reuse	8/22/2005
Advanced Modeling Verifies Backplane Designs	8/15/2005
An Efficient Approach for Modeling Feedback Systems	8/8/2005
How Verilog-AMS Accelerates Transistor Modeling	8/1/2005
Getting the Most from Multiprocessor SoC Design	7/20/2005
Improving Yield in RTL-to-GDSII Flows	7/11/2005
IBIS 4.1 Enhances Signal Integrity Modeling	7/4/2005
How to Improve Verification Planning	6/27/2005
Equivalency Checking Verifies Sequential Changes	6/20/2005
A Thermal-Aware IC Design Methodology	6/13/2005
Top-down Approach Speeds Mixed-Signal design	6/6/2005
Formal Approach Offers Verification "Salvation"	5/30/2005
How FPGA Packaging Drives Signal Integrity	5/16/2005
A Guide to Better EMC for PC-Board Design	5/9/2005
The "Why" and "What" of Algorithmic Synthesis	5/2/2005
Getting the Most Out of Formal Analysis	4/25/2005
Model-Based Approach Allows Design for Yield	4/18/2005
What Designers Need to Know About TCAD	4/4/2005
A Methodology for IC Power Grid Design	3/11/2005
Indicators Help Manage Coverage-Driven Verification	2/21/2005
Coverage Is the Heart of Verification	2/14/2005
IP Reuse Requires a Verification Strategy	2/8/2005
How Memory Architectures Affect System Performance	1/31/2005
Techniques for Reducing Signal-Integrity Pessimism	1/24/2005
Reducing False Errors in Clock-Domain Crossing Analysis	1/17/2005
What Platform ASICs Are and When to Use Them	1/10/2005
An Introduction to PLM for EDA	12/28/2004
Mixed-Level Modeling Allows IC Virtual Prototypes	12/16/2004
How Statistical Sensitivity Makes Designs Manufacturable	12/9/2004
The Why, Where and What of Low-Power SoC Design	12/2/2004
"Wrap" Your Cores to Enable SoC Test	11/24/2004
Use Macrocells to Automate Analog/Mixed-Signal Design	11/19/2004
How Infineon implemented OpenAccess	11/11/2004
Application Engine Synthesis Offers New Design Approach	11/5/2004
A Primer on Processor-based Emulation	10/21/2004
Catalytic Adds Key Piece to ESL Puzzle	10/20/2004
How to Evaluate Test Compression Methods	10/7/2004
How Diagnostics Accelerate Nanometer Yield Ramp	10/1/2004
Converting Floating-Point Applications to Fixed-Point	9/24/2004
How Power-Aware Test Improves Reliability and Yield	9/15/2004
Symmetric Design Technique Facilitates Power Analysis	9/3/2004
Correlating Behavioral Cycle Time with HDL Simulation	8/27/2004
Improving Yields without Compromising Area	8/13/2004
Modeling and Design Techniques Reduce 90nm Power	8/6/2004
Using Formal Verification to Create Robust IP	7/30/2004
A Scalable Approach to Speeding Physical Verification	7/21/2004
Minimize IC Power without Sacrificing Performance	7/15/2004
How to Choose a Verification Methodology	7/9/2004
An Introduction to Open-Source Hardware Development	7/1/2004
Approaches to Accelerated HW/SW Co-Verification	6/25/2004
Power Integrity Requires Global I/O SSO Analysis	6/16/2004
Techniques for Verifying Multiprocessor Designs	6/14/2004
At-Speed Testing Made Easy	6/3/2004
Formal Approach Eases Multiple Clock Design	5/20/2004
How to Manage a Derivative SoC Project	4/30/2004
How Specifications Drive Analog Design	4/23/2004
An FPGA Primer for ASIC Designers	4/15/2004
A Look Inside Behavioral Synthesis	4/8/2004
Bringing Assertions into Hardware-Assisted Verification	4/2/2004
A Look Inside Electronic System Level (ESL) Design	3/26/2004
A New Vision of "Scalable" Verification	3/18/2004
Firmware Friendly Chip-Level Design Techniques	3/12/2004
A New Approach to Nanometer Delay Modeling	3/4/2004
SystemVerilog Enhancements for All Chip Designers	2/26/2004
Quality of Silicon Metric Gauges EDA Tool Success	2/12/2004
Reshaping the SoC Power Design Flow	2/6/2004
How SystemVerilog Aids Design and Synthesis	1/27/2004
GDSII-based Flow Speeds Mask Data Preparation	1/9/2004
Lithography Advances on Multiple Fronts	1/5/2004
Evaluating and Improving Emulator Performance	1/3/2004
Achieving Signal Integrity for ASICs, PCBs and Packages	12/19/2003
Nanometer IC Routing Requires New Approaches	12/12/2003
Write Your Own PCB Database Translator	12/5/2003
"Best practices" Improve Hierarchical Design Constraints	12/1/2003
How Designers Can Increase Parametric Yield	11/21/2003
IC-Package Co-design Supports Flip-Chips	11/13/2003
VHDL-200x Improves Design and Verification Productivity	11/7/2003
Play It Again with "Replayable" Floorplans	10/31/2003
A Methodology for Minimizing Leakage Current	10/10/2003
Jeda Language Simplifies Hardware Verification	10/3/2003
Maximize Your Utilization of Acceleration and Emulation	9/26/2003
"Software compiled" Methodology is Needed for ESL	9/18/2003
Declarative Programming Language Simplifies Hardware Design	9/18/2003
Rethinking Test at 130 Nanometers and Below	9/12/2003
Write Your Own PCB Design Rule Checker	9/5/2003
Configurable Processors or RTL: Evaluating the Tradeoffs	8/27/2003
Right on Time: Requirements for Advanced Custom Design	8/22/2003
RTL Design Handoff Is Ready	8/22/2003
Tips for Firmware-friendly Register Design	8/14/2003
Accellera's ALF Language Lets Designers Control Libraries	8/8/2003
Techniques for Energy-Efficient SoC Design	7/24/2003
Hierarchical Design Methodology Supports Complex FPGAs	7/17/2003
Managing Loss in High-speed PCBs	7/7/2003
Techniques to Make Clock Switching Glitch Free	6/26/2003
Using "Empty Space" for IC Congestion Relief	6/19/2003
Maximize CPU Power for Physical Verification	6/13/2003
Low-power Design Techniques Span RTL-to-GDSII Flow	6/9/2003
An Overview of SystemVerilog 3.1	5/21/2003
How to Generate At-speed Scan Vectors	5/9/2003
A System-Level Methodology for Low-Power Design	5/2/2003
Making Hardware Modules Firmware-friendly	4/25/2003
Design for Verification Methodology Allows Silicon Success	4/18/2003
How Performance Analysis Aids System Design	4/11/2003
How Tensilica Verifies Processor Cores	4/4/2003
Why You Need RTL Virtual Prototyping	3/28/2003
Simple Techniques for Making Verification Reusable	3/21/2003
What Designers Need to Know about Structural Test	3/6/2003
SystemC Verification Library Speeds Transaction-Based Verification	2/24/2003
Reaching for the 1 GHz Ring	2/10/2003
Making Storage Elements Firmware Friendly	2/5/2003
It's About Time: Charting a Course for Unified Verification	1/28/2003
Crosstalk Glitch Analysis: How to Get it Right	1/17/2003

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