Regular columns include: Industry Viewpoint, standards, libraries, programmable logic, design and verification languages, physical implementation, and test.

Articles Online
Determine the Best Verification Solution for the Task	8/1/2011
Routing Technologies for 28nm and Beyond	8/1/2011
SOC Ecosystems Become More Tightly Integrated	8/1/2011
Analog Circuits Benefit from Scaling Trends	4/1/2011
EDA Tools for 3D IC Design	4/1/2011
Get the Lowdown on Accellera's VIP and UVM	4/1/2011
In IP We Trust?	4/1/2011
System-Level Design: Five Likely 2011 Trends	4/1/2011
The (Design) House Always Wins: How DFM Improves the Odds of Tape-Out Success	4/1/2011
The Missing Pieces in Power Modeling; Who's Going to Provide Them	4/1/2011
Aggregation Drives Successful IP Reuse	8/1/2005
Good Engineering Practices Minimize Design-Porting Effort	8/1/2005
IC Economics 101	8/1/2005
Intermediate Verification Model Bridges High and Low Levels of Abstraction	8/1/2005
Shape The Design of Wireless Chips	8/1/2005
A Tale of Two Languages: SystemC and SystemVerilog	6/1/2005
Advantages Abound for a Conversion-Free, Low-Cost Path to Volume Production	6/1/2005
In Search of an ESL Design Methodology	6/1/2005
IP Reuse Gets a Reality Check	6/1/2005
Manage Complexity in Nanometer SoC Designs	6/1/2005
Navigating the Silicon Jungle: FPGA or ASIC?	6/1/2005
Start at the Top to Reduce Re-Spins for Analog-Digital Chips	6/1/2005
Guidelines to Maximize the Performance of Verilog-AMS/VHDL-AMS Behavioral Modeling	5/1/2005
It’s All about Dollars and Cents	5/1/2005
Math Does Matter in Analog Chip Design	5/1/2005
On-Chip Nonvolatile Memory Proves Ideal for Consumer Applications	5/1/2005
SPIRIT: Structure for Packaging, Integrating, and Re-Using IP within Tool Flows	5/1/2005
Design FPGA-Based DSPs for Performance and Power	3/1/2005
Speed SoC Software with Coprocessor Synthesis	3/1/2005
Take Designs from Algorithms to Artwork	3/1/2005
The Meaning of ESL Invites Confusion and Competition	3/1/2005
Use Co-Simulation for the Functional Verification of RTL Implementations	3/1/2005
3D SoC Design Makes Its Debut	1/1/2005
Microcontroller Design Gets Revamped	1/1/2005
Take The Next Productivity Leap	1/1/2005
Debugging IP-laden Designs	11/1/2004
Design for Volume	11/1/2004
Logically Flashing: Mixed-Signal Verification for Flash Modules Using Co-Simulation	11/1/2004
Mixed HDLs plus HVL: Part 2, Using Specman Elite in a Mixed Verilog/VHDL Chip Verification Environment	11/1/2004
Delay Testing for Nanometer Chips	9/1/2004
Designing with Real Intent’s Verix	9/1/2004
Embedded Logic Analyzer Speeds SoPC Design	9/1/2004
FPGA Tools: Field Programmable May No Longer Imply Short Develop Times	9/1/2004
Hot chips? ... Not! Efficient Power Management in the 90-nm Foundry Reference Flow	9/1/2004
Mixed HDLs plus HVL: Part 1, Using Specman Elite in a Mixed Verilog/VHDL Chip Verification Environment	9/1/2004
Analog PDK 101	7/1/2004
Caution: Clock Crossing	7/1/2004
FPGAs Go, Go, Go: Solving the FPGA Timing Closure Challenge for High-Speed Designs	7/1/2004
Structured ASICs: A Reality Check	7/1/2004
Verification Tools: Adding More Tools Improves the Probability of Silicon Success	7/1/2004
Easing Today’s Verification Language Bedlam	5/1/2004
Electronic System-Level (ESL) Tools	5/1/2004
ESL Bridges Design and Verification	5/1/2004
Navigating the Mixed-Signal Maze	5/1/2004
Putting the e into Elegant Verification	5/1/2004
FPGA Helps a Battlebot Rock On	3/1/2004
From IC to I See: The CMOS Imager Challenge	3/1/2004
Integrating Complex I/O in an SoC	3/1/2004
Roll Your Own Micro	3/1/2004
Analog Hard IP Made Portable	1/1/2004
Assertions Enter the Verification Arena	1/1/2004
C Models Speed Co-Design	1/1/2004
Enabling Signal Conditioning Circuitry	1/1/2004
Hardware Tools for Design	1/1/2004

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