EE Times Planet Analog.com, an EE Times online community, is the resource for analog and mixed/signal technology. Led by industry guru Stephen Ohr, this web site features up-to-the-minute news; exclusive user interviews, feature articles, commentary; and a regular online poll. The Technology Insights section is intended to provide management and engineering insight on technology trends, and assess their impact on analog and mixed-signal design. The site also includes industry resources and new product listings, in addition to an events calendar.

Articles Online
ADC Basics-Part 5: Key ADC Specifications for System Analysis	1/3/2013
Debunking Myths About Analog IP at 20nm	12/3/2012
ADC Basics-Part 4: Using Delta-Sigma ADCs in Your Design	11/29/2012
ADC Basics-Part 1: Does Your ADC Work in the Real World?	8/27/2012
Common Inter-IC Digital Interfaces for Audio Data Transfer	6/1/2012
Reducing EMI by Using Spread Spectrum Techniques	4/27/2012
An Overview of the JESD204 Standard for Analog/ Digital Converters	4/25/2012
Survival Guide to High-Speed ADC Digital Outputs	3/2/2012
Calibrating Amplifiers and ADCs in SOCs	2/5/2012
Applying the Interrupt Features of a MEMS Accelerometer	12/15/2011
Improve DAC Integral Non-Linearity Through Gain Correction	10/14/2011
Problems and Pitfalls with Signal Integrity at 10Gbps and Beyond	9/23/2011
Electrostatic Discharge Testing Standards: Understanding and Comparing the Differences	9/12/2011
Analog IP for Multimedia SOCs: An Eye on a World of Essential Analog Features	3/22/2011
Reducing EMI in Digital Systems Using Spread Spectrum Clock Generators: Part 2	3/3/2011
Reducing EMI in Digital Systems Using Spread Spectrum Clock Generators: Part 1	2/25/2011
Design Considerations in the Analog Signal Chain: Part 2	2/4/2011
Design Considerations in the Analog Signal Chain: Part 1	1/30/2011
Mixed-Signal Designs: The Benefits of Digital Control of Analog Signal Chains	1/15/2011
Using PSpice to Analyze Amplifier Loop Stability: Part 2	1/13/2011
Using PSpice to Analyze Amplifier Loop Stability: Part 1	1/8/2011
Advanced ADCs Deliver Very High Sample Rates, Resolution, and with Low Power	1/1/2011
Understanding the Basics of PLL Frequency Synthesis	12/23/2010
The Basics of SerDes for Interfacing	9/16/2010
Achieve Higher Accuracy Using Mixed-Signal FPGA Calibration	12/4/2008
Signal Integrity Approaches Meet the Multi-Gbps Design Challenge	3/25/2007
Improve Analog/Mixed-Signal Simulator Analysis Using Real-World, Hardware-Generated Ddata	3/12/2007
Selecting PLLs for ASIC Applications Requires Tradeoffs	9/24/2003
Programmable Logic Devices Offer Coprocessor Muscle for High Bandwidth Image Processing: Part 1	9/10/2003
Programmable Logic Devices Offer Coprocessor Muscle for High Bandwidth Image Processing: Part 2	9/9/2003
Clock Domain Modeling is Essential in High Density SoC Design	6/6/2003

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