June 12, 2007 -- The integrated end-point block for PCI Express in the Virtex-5 FPGA provides the benefits of an ASSP with the flexibility of an FPGA. Join this webcast and see how to implement a memory storage example on the Virtex-5 and how with this reference design you can leverage and take advantage of the programmable features in an FPGA for backplane, cabled and other types of designs.
Discover how the complete Xilinx solution for PCI Express including Virtex-5 development kit will quickly and efficiently get you started on a Virtex-5 design using PCI Express.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: EE Times Education & Training, TechOnLine, Xilinx, Virtex-5 FPGAs, field programmable gate arrays, PCI Express, PCIe,
336/22858 6/12/2007 1313 300
Subscribe to SOCcentral's SOC Explorer Newsletter and receive news, article, whitepaper, and product updates bi-weekly.