April 7, 2009 -- Deciding which variant of DDR memory to use in your design is a balance of speed, power consumption, complexity and cost. Many designers are facing the migration from DDR1 to DDR2, DDR2 to DDR3, or DDR to LPDDR. In each situation, the key challenges are in probing, parametric and protocol characterization, and guaranteeing interoperability. Are you are able to make repeatable, accurate measurements? Will your design survive a change in DRAM vendor? This presentation reviews the latest DDR trends, tips for ensuring interoperability, and the latest measurement techniques for characterizing and validating your memory design.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: Agilent Technologies, EE Times Education & Training, TechOnLine, embedded system design, DDR memory, testing, EDA tools,
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