October 14, 2009 -- To meet the relentless demand for improved feature sets and functionality in today's advanced cellular baseband and multimedia chips, modern SOCs require more powerful processing capabilities than ever before. In the same breadth, these SOCs are expected to operate within the same power budget allocated to preceding, less complex chipsets, particularly for mobile applications.
This CEVA webinar will deliver a fresh perspective on the main challenges involved in designing an advanced SOC while maintaining low-power consumption. It will provide insights into how SOC architects and designers can build state-of-the art SOCs for low-power requirements using different techniques and processor architectures.
Topics to be covered:
Future challenges in low-power SOC design.
Key concepts in building an advanced processor architecture for low power requirements.
Current trends and techniques used in low power processor architectures.
Implementation and verification flow of processors designed to meet low-power requirements.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, power analysis, low power design, low-power design, system-on-chip, SoC,
336/29691 10/14/2009 1853 129
Designer's Mall
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