Page loading . . .

  
 Category: Vendor Webcasts: Archived Webcasts: Thursday, May 23, 2013
Best Practices and Methods for Mixed-Signal Verification   Featured
Sponsor: Cadence Design Systems, Inc.
Webcaster: EE Times Education & Training
 Printer friendly
 E-Mail Item URL

November 18, 2009 -- Is mixed-signal verification a major bottleneck within your IC design and verification flow? Are you part of an analog/ mixed-signal design team that is required to deliver a high-quality functional "digital-only" simulation net list to a digital verification organization as part of SoC verification? If you answered yes to these questions, attend this webinar and learn how Cadence' Services can help you.
  • Reduce risk and boost verification productivity to obtain first-pass functional silicon.
  • Establish a scalable mixed-signal functional verification methodology.
  • Improve the quality of block signoff (compliance) and signal-path verification, thereby increasing the chance of first-pass spec-compliant silicon.

This webinar will introduce you to the following packaged services offerings from Cadence and how they can best be applied to meet your mixed-signal verification needs:
  • Mixed-signal functional verification – Behavioral modeling is the key technology to enable comprehensive mixed-signal functional verification. Cadence Services has been on the leading edge of behavioral modeling development as applied to mixed-signal functional verification for several years. This service will enable any IC mixed-signal design and verification organization to establish verification capability for an AMS flow (uses analog/ mixed-signal simulation) and DMS flow (uses digital-ONLY simulation).
  • Mixed-signal signal-path (spec) verification – Cadence Services will work with you to evaluate your current signal-path verification methods for the purpose of improving your signal-path verification process. This service focuses on block-level specifications and how to model this behavior to increase simulation throughput.


Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, functional verification, mixed signal design, mixed-signal design, Cadence Design Systems, EE Times Education & Training, TechOnLine,
336/30108 11/18/2009 2140 180


Designer's Mall
1.757813E-02



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
258.336  9.179688E-02