December 16, 2010 -- With 150-MHz performance and advanced DSP instructions, NXP's Cortex-M4 based LPC4300 series combines excellent signal processing performance with all the benefits of a microcontroller including integrated interrupt control, low-power modes, low-cost debug and ease-of-use. By taking advantage of NXP's asymmetrical dual-core Cortex-M0 subsystem, developers can off-load many of the data-movement and I/O-handling duties that can drain the bandwidth of the Cortex-M4 core. NXP's unique configurable peripherals such as the State Configurable Timer and Serial GPIO also off-load processor bandwidth while providing maximum I/O flexibility to the developer.
Attendees will learn about:
-M4 digital signal processing (DSP) and floating-point capabilities
NXP's optimized memory architecture to support Cortex-M4 performance
NXP's industry first Cortex-M0 subsystem processor
Advances in embedded tools to support asymmetrical dual-core architectures
NXP's unique configurable peripherals
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: embedded systems, embedded system design, DSP, digital signal processing, digital signal processors, microprocessors, MPUs, IP, intellectual property, cores, ARM Cortex,
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