Page loading . . .

  
 Category: Vendor Webcasts: Archived Webcasts: Saturday, May 18, 2013
Tackle Your Next High-Speed Serial Design with Comprehensive Solutions from Xilinx   Featured
Sponsor: Xilinx, Inc.
Webcaster: EE Times Education & Training
 Printer friendly
 E-Mail Item URL

March 28, 2012 -- Discover how Xilinx provides the most comprehensive high-speed serial design solutions to satisfy the insatiable bandwidth requirements of today's most demanding applications. Xilinx 7 series transceivers offer the industry's best signal integrity and highest aggregate transceiver bandwidth. Xilinx also offers a complete suite of tools and IP to enable designers to maximize their productivity and reduce time-to-market barriers. In this webcast we walk through the most common design steps and explore how our scalable serial solutions enable faster design completion.

Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.

Keywords: FPGAs, field programmable gate arrays, FPGA design, Xilinx, EE Times Education & Training
336/38049 3/28/2012 567 24


Designer's Mall
0.015625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
258.336  0.078125