Page loading . . .

  
 Category: Vendor Webcasts: Archived Webcasts: Sunday, May 19, 2013
Designing and Testing Secure Intelligent Systems   Featured
Sponsor: Wind River
Webcaster: OpenSystems Media
 Printer friendly
 E-Mail Item URL

April 18, 2012 -- Join Wind River and Mocana as we discuss best practices for deigning and testing secure intelligent systems, to ensure that convenience does not go hand-in hand with opening the door to new attack vectors that might be exploited by unscrupulous hackers.

By attending this 45 minute webinar you will learn:
  • How the threat landscape has changed in recent years.
  • How to design and build secure intelligent devices that will stand up to real-world threats.
  • How to thoroughly test your embedded software prior to shipment and avoid nasty surprise in the field.


Go directly to the OpenSystems Media webcast site to view this presentation. Registration may be required.

Keywords: computer system design, general-purpose computers, special-purpose computers, embedded system design, embedded systems, EDA, EDA tools, electronic design automation, software development tools, Wind River, OpenSystems Media,
336/38219 4/18/2012 582 59


Designer's Mall
1.953125E-02



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
258.336  8.203125E-02