June 27, 2012 -- When designing mobile devices, it is critical to implement technologies that will future-proof your design, minimize BOM costs and board space, and maintain or improve performance. The MIPI Alliance Low Latency Interface (LLI) and M-PHY are two technologies that can help future-proof your design while giving it competitive advantages in terms of cost, board space, performance, and time-to-market. This webinar presents a case study describing how LLI can be used to minimize DRAM footprint on a mobile phone system board. Particular attention will be paid to real-world implementation issues, such as clock domain, power and voltage management as well as integration with SOC interconnect fabrics.
This webinar will teach you:
What the LLI and M-PHY technologies are, and best practices for implementation.
How LLI is different than other chip-to-chip interface standards, such as USB and PCIe.
How the LLI point-to-point interconnect can benefit multi-chip systems.
How the LLI controller and M-PHY IP can reduce the silicon footprint on your board.
How LLI can reduce individual BOM and multi-product platform costs.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: embedded system design, embedded systems, IP, intellectual property, cores, Mobile Industry Processor Interface, MIPI, Synopsys, EE Times Education & Training
336/38687 6/27/2012 630 25
Designer's Mall
1.953125E-02
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