July 19, 2012 -- When facing the challenging task of implementing constrained random stimulus or functional coverage in their testbenchs, VHDL designers used to make difficult choice between "reinventing the wheel" (writing appropriate code from scratch) and !using a square wheel! (using SystemVerilog for verification). This webinar demonstrates a third option; the Open Source VHDL Verification Methodology (OS-VVM), a set of VHDL packages that provide reliable, field-tested procedures and functions handling randomization and functional coverage. Attendees will learn about the structure and use of OS-VVM packages, paying special attention to Smart Coverage that combines random stimulus and functional coverage to provide faster verification.
Go directly to the Aldec, Inc. webcast site to view this presentation. Registration may be required.