August 2, 2012 -- Mobile communications, multimedia and consumer SOCs must achieve the highest performance while consuming the minimal amount of energy to achieve longer battery life and fit into lower cost packaging. Logic libraries with a wide variety of voltage thresholds (VTs) and gate channel lengths provide an efficient method for managing energy consumption.
This webinar focuses on:
How combining innovative power management techniques using multiple VTs/ channel lengths in different SOC logic blocks delivers the optimal trade-off in SOC watts per gigahertz.
Ways to maximize system performance and minimize cost while slashing power budgets of SOC blocks operating at different clock speeds.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, low power design, low-power design, power analysis, power optimization, Synopsys, EE Times Education & Training
336/38860 8/2/2012 595 25
Designer's Mall
1.599121E-02
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