| Making Mobile SOC Device Design Easier with System IP Featured | Sponsor: Sonics, Inc. Webcaster: EE Times Education & Training
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August 21, 2012 -- There is growing demand for the complex SOCs driving the cloud computing revolution. More complex SOCs typically integrate many IP blocks from multiple vendors. At the same time, the IP blocks themselves are becoming increasingly complex, making efficient architecture planning, design implementation, integration and verification more and more difficult.
As a result, SOC architects are having a hard time executing flawless designs while meeting the schedule demands created by time-to-market pressures. Designers are inundated with critical concerns such as how do we deal with IP from multiple vendors? How do we test and verify that all of these blocks work together? How can we verify system performance? How can we optimize power? What is the impact on software?
This webinar will focus on how Sonics can help designers deal with these issues through the use of advanced System IP. System IP includes on-chip networks, memory subsystems, system performance analysis capability, and power management. Sonics will discuss how to use System IP to increase performance, significantly improve power management, decrease costs and accelerate time-to-market for complex SOCs.
Registrant will learn:
- How to integrate and optimize multiple IP block for complex SOC designs to meet the requirements for system performance, power and cost.
- How to efficiently support system testing and verification.
- How to seamlessly integrate IP cores from multiple vendors.
- How System IP can help accelerate your next design cycle.
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Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
| | Keywords: ASICs, ASIC design, IP, intellectual property, cores, on-chip interconnect, network-on-chip, NoC, Sonics, EE Times Education & Training
| | 336/38944 8/21/2012 580 134 | |
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| | 0.015625 |
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