This 9-minute video by John Aynsley from Doulos is an introduction to version 1.2 of the VMM (Verification Methodology Manual) for SystemVerilog, highlighting the new features of VMM 1.2 and the overall conceptual framework. It discusses such topics as ... read more

This 9-minute video by John Aynsley from Doulos, describes ten things you should know about OVM, the Open Verification Methodology for SystemVerilog. This video gives you a top-level technical overview of OVM without diving down into too much language ... read more

This 9-minute video by Jonathan Bromley from Doulos explains the mechanisms for observing activity in VMM and OVM test benches for the purposes of checking and coverage collection and deploying verification IP, registering VMM callbacks, and observatio ... read more

This 8-minute video by Jonathan Bromley from Doulos explains how Transaction Level Modeling techniques are used to communicate between components in OVM, the Open Verification Environment. It covers connections in RTL Verilog, a BFM task in testbench, ... read more

This 10-minute video by John Aynsley from Doulos describes the OSCI SystemC TLM-2.0 base protocol checker freely available from Doulos under an open source software license. It covers the interoperability of layer and base protocols, and inserting the ... read more

In this 10-minute video by John Aynsley from Doulos, the RTL (Register Transfer Level) and TLM (Transaction Level Modeling) abstractions are compared, and also the AT (Approximately Timed) and LT (Loosely Timed) coding styles of the OSCI SystemC TLM-2. ... read more

This 10-minute video by John Aynsley from Doulos provides an introduction to the OSCI TLM-2.0 Standard, which provides interoperability between SystemC transaction-level models that are integrated around a memory-mapped bus as part of an SOC. Particula ... read more

This 10-minute video by John Aynsley, CTO for Doulos, discusses the difference between VHDL and SystemVerilog. It compares the use of VHDL, Verilog and SystemVerilog in FPGA and ASIC design, as well as in FPGA and ASIC verification and verification IP ... read more

This 10-minute video by John Aynsley, CTO for Doulos, discusses the difference between SystemC and SystemVerilog. This video includes a brief description of these two EDA language standards, discussing the reasons for using SystemC and transaction-leve ... read more

May 31, 2012 -- For decades, multitudes of embedded machines have been specialized islands of vertical fixed-function intelligence with unique attributes. As the need and opportunity evolves to connect and coordinate between these embedded machi ... read more